1. Owen Long, UCSB VERTEX ‘98 Santorini, Greece The BaBar Silicon Vertex Tracker Owen Long University of California, Santa Barbara for the BaBar Collaboration

2. Owen Long, UCSB VERTEX ‘98 Santorini, Greece PEP-II and the BaBar Experiment Physics Objective: CP violation in B meson decays. Overdetermine the parameters of the CKM quark mixing matrix. Physics Objective: CP violation in B meson decays. Overdetermine the parameters of the CKM quark mixing matrix. Experimental Approach: High-luminosity e + e - collider with Upsilon(4s) center-of-mass energy. B and anti-B mesons produced coherently. CP asymmetries depend on  t between B decays. Time-integrated CP asymmetries vanish. Measurement of B decay points is essential. Asymmetric beam energies boost Upsilon(4s) in lab (  =0.56). Experimental Approach: High-luminosity e + e - collider with Upsilon(4s) center-of-mass energy. B and anti-B mesons produced coherently. CP asymmetries depend on  t between B decays. Time-integrated CP asymmetries vanish. Measurement of B decay points is essential. Asymmetric beam energies boost Upsilon(4s) in lab (  =0.56). e - beam direction zz Upsilon(4s) decay point B 0 decay point B 0 decay point

3. Owen Long, UCSB VERTEX ‘98 Santorini, Greece SVT Institutions USA: Lawrence Berkeley National Laboratory Stanford University University of California, Santa Barbara University of California, Santa Cruz University of California, San Diego University of Wisconsin Italy: Ferrara Milan Pavia Pisa Torino Trieste

4. Owen Long, UCSB VERTEX ‘98 Santorini, Greece SVT Design Requirements and Constraints Performance Requirements  z resolution < 130  m. Single vertex resolution < 80  m. Stand-alone tracking for Pt < 100 MeV/c. Performance Requirements  z resolution < 130  m. Single vertex resolution < 80  m. Stand-alone tracking for Pt < 100 MeV/c. PEP-II Constraints Permanent dipole (B1) magnets at +/- 20 cm from IP. Polar angle restriction: 17.2 0 <  < 150 0. Must be clam-shelled into place after installation of B1 magnets Bunch crossing period: 4.2 ns (nearly continuous interactions). Radiation exposure at innermost layer (nominal background level): Average: 33 kRad/year. In beam plane: 240 kRad/year. SVT is designed to function in up to 10 X nominal background. PEP-II Constraints Permanent dipole (B1) magnets at +/- 20 cm from IP. Polar angle restriction: 17.2 0 <  < 150 0. Must be clam-shelled into place after installation of B1 magnets Bunch crossing period: 4.2 ns (nearly continuous interactions). Radiation exposure at innermost layer (nominal background level): Average: 33 kRad/year. In beam plane: 240 kRad/year. SVT is designed to function in up to 10 X nominal background.

5. Owen Long, UCSB VERTEX ‘98 Santorini, Greece The BaBar Silicon Vertex Tracker 5 Layers of double-sided, AC-coupled Silicon. Custom rad-hard readout IC (the AToM chip). Low-mass design. ( Pt < 2.7 GeV/c 2 for B daughters) Stand-alone tracking for slow particles. Inner 3 layers for angle and impact parameter measurement. Outer 2 layers for pattern recognition and low Pt tracking. 5 Layers of double-sided, AC-coupled Silicon. Custom rad-hard readout IC (the AToM chip). Low-mass design. ( Pt < 2.7 GeV/c 2 for B daughters) Stand-alone tracking for slow particles. Inner 3 layers for angle and impact parameter measurement. Outer 2 layers for pattern recognition and low Pt tracking. 40 cm 30 cm 20 cm

6. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Space Frame and Support Cones

7. Owen Long, UCSB VERTEX ‘98 Santorini, Greece SVT Geometry (Arched wedge wafers not shown) Be Beam pipe 1.0 % X 0 10 cm Layer Radius 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 511.4 to 14.6 cm Layer Radius 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 511.4 to 14.6 cm

8. Owen Long, UCSB VERTEX ‘98 Santorini, Greece SVT Modules Z-Side Phi-Side Si Wafers Carbon/Kevlar fiber Support ribs High Density Interconnect (mechanical model) Micro-bonds Flexible Upilex Fanout Fanout Properties: < 0.03 % X 0 0.52 pF/cm Fanout Properties: < 0.03 % X 0 0.52 pF/cm

9. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Ringframe Fixtures Ringframes protect Si wafers and High Density Interconnects (HDIs) during testing. “Parking lot” on Fanout enables wafer tests without bonding. Bonds for strips with faults plucked before bonding to HDI. “Parking lot” on Fanout enables wafer tests without bonding. Bonds for strips with faults plucked before bonding to HDI. Fanout is cut, glued, and bonded to HDI after wafer testing. 1/2 modules are tested again before module assembly. Fanout is cut, glued, and bonded to HDI after wafer testing. 1/2 modules are tested again before module assembly.

10. Owen Long, UCSB VERTEX ‘98 Santorini, Greece SVT High Density Interconnect AToM Chips Upilex Fanout Mounting Buttons Berg Connector Flexible Tail (testing version) Functions: Mounting and cooling for readout ICs. Mechanical mounting point for module. Functions: Mounting and cooling for readout ICs. Mechanical mounting point for module. Features: AlN substrate. Double sided. Thermistor for temp. monitor. 3 different models. Features: AlN substrate. Double sided. Thermistor for temp. monitor. 3 different models.

11. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Silicon Wafers Features: Manufactured at Micron. 300  m thick. 6 different wafer designs. n - bulk, 4-8 k  cm. AC coupling to strip implants. Polysilicon Bias resistors on wafer, 5 M  Features: Manufactured at Micron. 300  m thick. 6 different wafer designs. n - bulk, 4-8 k  cm. AC coupling to strip implants. Polysilicon Bias resistors on wafer, 5 M 

12. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Silicon Wafers Bias ring p + Implant Al p + strip side P-stop n + Implant Polysilicon bias resistor Polysilicon bias resistor Edge guard ring Edge guard ring n + strip side 50  m 55  m

13. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Measured Wafer Characteristics Strip Properties n-siden-side n-side p-side Strip Pitch:50  m55  m105  m50  m Inter-strip C:1.1 pF/cm1.0 pF/cm 1.0 pF/cm1.1 pF/cm AC decoupling C:20 pF/cm22 pF/cm34 pF/cm 43 pF/cm Implant-to-back C:0.19 pF/cm0.36 pF/cm0.17 pF/cm Bias R:4 to 8 M  4 to 8 M  4 to 8 M  4 to 8 M  Strip Properties n-siden-side n-side p-side Strip Pitch:50  m55  m105  m50  m Inter-strip C:1.1 pF/cm1.0 pF/cm 1.0 pF/cm1.1 pF/cm AC decoupling C:20 pF/cm22 pF/cm34 pF/cm 43 pF/cm Implant-to-back C:0.19 pF/cm0.36 pF/cm0.17 pF/cm Bias R:4 to 8 M  4 to 8 M  4 to 8 M  4 to 8 M  Bulk Properties Bias current:0.1 to 1.0  A Bulk current:0.1 to 1.0  A Depletion voltage: 35 to 45 V Bulk Properties Bias current:0.1 to 1.0  A Bulk current:0.1 to 1.0  A Depletion voltage: 35 to 45 V

14. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Detector-Fanout Assemblies Status: All wafers are glued to fanouts, bonded, and tested. Over 0.3 million bonds. Status: All wafers are glued to fanouts, bonded, and tested. Over 0.3 million bonds. Fault Types: Pinhole - Break in the AC coupling capacitor, short between metal and implant. P-stop short (DC) - Bond foot breaks through oxide layer shorting metal and p-stop. High current (DC) - Low value for bias resistor. Unbondable - Damaged or obstructed bond pad, rework not possible. Fault Types: Pinhole - Break in the AC coupling capacitor, short between metal and implant. P-stop short (DC) - Bond foot breaks through oxide layer shorting metal and p-stop. High current (DC) - Low value for bias resistor. Unbondable - Damaged or obstructed bond pad, rework not possible. FaultChannels Pinhole 1 - 2 % DC-fault 1 - 2 % Other 1 % Total faults: 2 - 4 % FaultChannels Pinhole 1 - 2 % DC-fault 1 - 2 % Other 1 % Total faults: 2 - 4 %

15. Owen Long, UCSB VERTEX ‘98 Santorini, Greece The AToM Chip Features: 128 Channels per chip Rad-Hard CMOS process (Honeywell) Simultaneous –Acquisition –Digitization –Readout Sparsified readout Time Over Threshold (TOT) readout Internal charge injection Features: 128 Channels per chip Rad-Hard CMOS process (Honeywell) Simultaneous –Acquisition –Digitization –Readout Sparsified readout Time Over Threshold (TOT) readout Internal charge injection AToM = A Time Over threshold Machine Custom Si readout IC designed for BaBar by: LBNL INFN-Pavia UCSC Custom Si readout IC designed for BaBar by: LBNL INFN-Pavia UCSC 5.7 mm 8.3 mm

16. Owen Long, UCSB VERTEX ‘98 Santorini, Greece The AToM Chip CAL DAC Shaper Thresh DAC Comp PRE AMP TOT Counter Time Stamp Event Time Event Number Revolving Buffer 193 Bins Si Buffer Chan # Sparsification Readout Buffer C INJ C AC Serial Data Out Amp, Shape, Discr, Calib 5-bit CAL DAC (0.5 fC/count) 5-bit Thr DAC (0.05 fC/count) Shaping time 100 - 400 ns Amp, Shape, Discr, Calib 5-bit CAL DAC (0.5 fC/count) 5-bit Thr DAC (0.05 fC/count) Shaping time 100 - 400 ns Trigger Latency Buffer 15 MHz Sample rate Total storage = 12.7 us Trigger Latency Buffer 15 MHz Sample rate Total storage = 12.7 us TOT, Tstamp, Buffering 4 bits TOT (logarithmic) 5 bits Hit Tstamp (67 ns/count) 4 buffers / channel TOT, Tstamp, Buffering 4 bits TOT (logarithmic) 5 bits Hit Tstamp (67 ns/count) 4 buffers / channel 15 MHz

17. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Threshold Scan Procedure Fix charge injection value Scan Threshold DAC (0-63)  1 Threshold DAC count = 10.5 mV  10.5 mV/count / Gain = 0.053 fC / count Fit Hit efficiency vs Threshold to Error Function  Width = Noise  50% point = Offset for Qinj Procedure Fix charge injection value Scan Threshold DAC (0-63)  1 Threshold DAC count = 10.5 mV  10.5 mV/count / Gain = 0.053 fC / count Fit Hit efficiency vs Threshold to Error Function  Width = Noise  50% point = Offset for Qinj Gain Measurement 3 threshold scans at different Qinj values Fit 50% point vs Qinj Slope is Gain (  thr/  Q in mV/fC) Intercept is Threshold DAC offset Gain Measurement 3 threshold scans at different Qinj values Fit 50% point vs Qinj Slope is Gain (  thr/  Q in mV/fC) Intercept is Threshold DAC offset Threshold Hits Offset Noise Qinj Counts Offset Counts Threshold DAC Offset

18. Owen Long, UCSB VERTEX ‘98 Santorini, Greece TOT and Charge Scan CAL DAC Injected Charge (fC) Time Over Threshold 1 MIP Scan calibration DAC (0-63) at a fixed threshold. Range of injected charge: 0 to 30 fC (1 MIP = 3.8 fC) Measure Time Over Threshold (TOT) response. Hit TOT stored in 4 bits (1-15). Scan calibration DAC (0-63) at a fixed threshold. Range of injected charge: 0 to 30 fC (1 MIP = 3.8 fC) Measure Time Over Threshold (TOT) response. Hit TOT stored in 4 bits (1-15).

19. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Measured Noise and Gain Chip Properties Threshold offset dispersion:14 mV or 440 ele Chip power consumption:0.57 W/chip,4.5 mW/chan Chip Properties Threshold offset dispersion:14 mV or 440 ele Chip power consumption:0.57 W/chip,4.5 mW/chan 100 ns200 ns400 ns AToM-I, test board:450 ele + 47 ele/pF375 ele + 45 ele/pF325 ele + 39 ele/pF AToM-II, test board:350 ele + 40 ele/pF275 ele + 35 ele/pF225 ele + 26 ele/pF AToM-I, Layer 2 mod: Phi-side1350 ele1200 ele1050 ele Z-side1050 ele 850 ele 750 ele AToM-I, Gain:190 mV/fC 235 mV/fC 200 mV/fC AToM-II, Gain: 300 mV/fC Total strip capacitance ranges from 11 to 37 pF. Threshold setting of 4 X Noise still well below 1 MIP ( about 20,000 ele ). 100 ns200 ns400 ns AToM-I, test board:450 ele + 47 ele/pF375 ele + 45 ele/pF325 ele + 39 ele/pF AToM-II, test board:350 ele + 40 ele/pF275 ele + 35 ele/pF225 ele + 26 ele/pF AToM-I, Layer 2 mod: Phi-side1350 ele1200 ele1050 ele Z-side1050 ele 850 ele 750 ele AToM-I, Gain:190 mV/fC 235 mV/fC 200 mV/fC AToM-II, Gain: 300 mV/fC Total strip capacitance ranges from 11 to 37 pF. Threshold setting of 4 X Noise still well below 1 MIP ( about 20,000 ele ). AToM-II measurements are preliminary.

20. Owen Long, UCSB VERTEX ‘98 Santorini, Greece AToM IC and Wafer Characteristics After Exposure to Radiation AToM-I Chip After exposure to 2.4 MRad with Co 60 source Gain dropped 0 to 20 % Power off during exposurePower on during exposure C=0 dNoise/dC C=0 dNoise/dC Noise Increase15 to 80 % 15 to 50 %5 to 10 % < 5% Only 3 chips tested. Will check this result with more tests. AToM-I Chip After exposure to 2.4 MRad with Co 60 source Gain dropped 0 to 20 % Power off during exposurePower on during exposure C=0 dNoise/dC C=0 dNoise/dC Noise Increase15 to 80 % 15 to 50 %5 to 10 % < 5% Only 3 chips tested. Will check this result with more tests. Silicon Wafers After exposure to 1 MRad of photons from a Co 60 source <17% increase in interstrip capacitance Current density <350 nA/cm 2, mostly generation at Si - insulator surface Silicon Wafers After exposure to 1 MRad of photons from a Co 60 source <17% increase in interstrip capacitance Current density <350 nA/cm 2, mostly generation at Si - insulator surface

21. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Production and Construction Silicon Wafers: All wafers in hand. Wafers glued to fanouts, bonded, and tested. Front-End Electronics: High Density Interconnect (HDI) substrate production nearly complete. 2 lots of AToM-I in hand. AToM-II testing underway. Several HDIs loaded, tested, and bonded to detectors. Mechanical: Support cones, space frame, and mounting rings complete. Ready to begin module assembly. Back-End Electronics: Production complete. Loading and testing. Estimated date of completion: Early March 1999. Silicon Wafers: All wafers in hand. Wafers glued to fanouts, bonded, and tested. Front-End Electronics: High Density Interconnect (HDI) substrate production nearly complete. 2 lots of AToM-I in hand. AToM-II testing underway. Several HDIs loaded, tested, and bonded to detectors. Mechanical: Support cones, space frame, and mounting rings complete. Ready to begin module assembly. Back-End Electronics: Production complete. Loading and testing. Estimated date of completion: Early March 1999.

22. Owen Long, UCSB VERTEX ‘98 Santorini, Greece PEP-II at SLAC The PEPII Collider at SLAC Luminosity: 3 x 10 33 to 10 34 cm -2 s -1 30 to 100 million Upsilon(4s) per year. Beams collided head-on (no crossing angle). Bunch crossing period: 4.2 ns Interactions effectively continuous. Permanent dipole magnets required close to interaction point. The PEPII Collider at SLAC Luminosity: 3 x 10 33 to 10 34 cm -2 s -1 30 to 100 million Upsilon(4s) per year. Beams collided head-on (no crossing angle). Bunch crossing period: 4.2 ns Interactions effectively continuous. Permanent dipole magnets required close to interaction point.

23. Owen Long, UCSB VERTEX ‘98 Santorini, Greece SVT Mechanical Features Carbon fiber Space Frame Carbon fiber support cones Brass cooling rings B1 dipole permanent magnet (inside support cone) B1 dipole permanent magnet (inside support cone) 109 cm 22 cm

24. Owen Long, UCSB VERTEX ‘98 Santorini, Greece SVT Mechanical Features Silicon wafers Carbon & Kevlar fiber support ribs

25. Owen Long, UCSB VERTEX ‘98 Santorini, Greece SVT Modules Layer Number of Wafers Total Phi-Strip Length Backward Forward Z-Strip Length 5b826.5 cm26.5 cm4.1 to 5.1 cm 5a826.5 cm25.1 cm4.2 to 5.1 cm 4b722.4 cm19.9 cm4.2 to 5.1 cm 3612.8 cm 12.8 cm7.0 cm 24 8.8 cm 8.8 cm4.8 cm 14 8.2 cm 8.2 cm4.0 cm 4a722.4 cm18.5 cm4.2 to 5.1 cm

26. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Silicon Wafers P-Stops n - Bulk n + Implant p + Implant Strip Pitch Silicon dioxide Aluminum Features: Manufactured at Micron. 300  m thick. 6 different wafer designs. n - bulk, 4-8 k  cm. AC coupling to strip implants. Polysilicon Bias resistors on wafer, 5 M  Features: Manufactured at Micron. 300  m thick. 6 different wafer designs. n - bulk, 4-8 k  cm. AC coupling to strip implants. Polysilicon Bias resistors on wafer, 5 M  Readout Pitch

27. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Wafer Specifications Used in Layers 1,2, and 3 Used in Layers 4 and 5

28. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Phi Side Readout Pitch, 1-3 100  m Pitch 50  m Pitch Phi side is 30 - 100 % half bonded due to E x B effect. 100 to 110  m readout pitch where charge is spread over more strips. 50 to 55  m readout pitch where charge is focused on fewer strips. Phi side is 30 - 100 % half bonded due to E x B effect. 100 to 110  m readout pitch where charge is spread over more strips. 50 to 55  m readout pitch where charge is focused on fewer strips. Compromise between Hit efficiency Signal to noise ratio and Hit resolution 2-Track resolution Compromise between Hit efficiency Signal to noise ratio and Hit resolution 2-Track resolution

29. Owen Long, UCSB VERTEX ‘98 Santorini, Greece SVT Data Transmission HDI Matching Card Kapton Tail Front Cables Si Wafers HDI Link DAQ Link Power Supplies MUX Power Back Cables Fiber Optic to DAQ HDI: High Density Interconnect. Mounting fixture and cooling for readout ICs. Kapton Tail: Flexible multi-layer circuit. Power, clock, commands, and data. Matching Card: Connects dissimilar cables. Impedance matching. HDI Link: Reference signals to HDI digital common. DAQ Link: Multiplex control, demultiplex data. Electrical -- optical conversion. HDI: High Density Interconnect. Mounting fixture and cooling for readout ICs. Kapton Tail: Flexible multi-layer circuit. Power, clock, commands, and data. Matching Card: Connects dissimilar cables. Impedance matching. HDI Link: Reference signals to HDI digital common. DAQ Link: Multiplex control, demultiplex data. Electrical -- optical conversion.

30. Owen Long, UCSB VERTEX ‘98 Santorini, Greece Calibration Internal charge injection used for Measuring Gain, Noise, and Threshold Offsets Identifying shorts and bad channels Examining Time Over Threshold (TOT) response Testing digital functionality Internal charge injection used for Measuring Gain, Noise, and Threshold Offsets Identifying shorts and bad channels Examining Time Over Threshold (TOT) response Testing digital functionality Charge injection circuit 5-bit DAC (0-63) 1 DAC count = 0.48 fC Range 0 - 30 fC (1 MIP = 4 fC) Charge injection circuit 5-bit DAC (0-63) 1 DAC count = 0.48 fC Range 0 - 30 fC (1 MIP = 4 fC) Calibration methods Threshold scan (Gain, Noise, Offsets) Charge scan (TOT response) Calibration methods Threshold scan (Gain, Noise, Offsets) Charge scan (TOT response)