1. Spring 08, Feb 28 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Retiming Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html

2. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)2 Retiming  Retiming is a function-preserving transformation of a synchronous sequential circuit.  Flip-flops are moved according to specific rules.  Original references:  C. E. Leiserson, F. Rose and J. B. Saxe, “Optimizing Synchronous Circuits by Retiming,” Proc. 3 rd Caltech Conf. on VLSI, 1983, pp. 87-116.  C. E. Leiserson and J. B. Saxe, “Retiming Synchronous Circuitry,” Algorithmica, vol. 6, pp. 5-35, 1991.

3. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)3 A Trivial Example: Reduced Hardware FF

4. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)4 Example 2: Faster Clock FF

5. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)5 Example 3: Reduced Flip-Flops FF

6. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)6 Applications of Retiming  Performance optimization  Area optimization  Power optimization  Testability enhancement  FPGA optimization

7. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)7 Fundamental Operation of Retiming  A retiming move in a circuit is caused by moving all of the memory elements at the input of a combinational block to all of its outputs, or vice- versa. Combinational logic FF Combinational logic FF ≡

8. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)8 A Correlator Circuit +++ ==== host Adder delay = 7 Comparator delay = 3 Flip-flop PI PO a1 a2a3 a4

9. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)9 Graph Model 777 3333 0 0 0 0 0 0 0 0 1 11 1 Vertex, vi, combinational, delay = d(vi), assumed unchanged by retiming d(host) = 0 Edge, e(vi,vj) or eij, weight wij = number of flip-flops between vi and vj h a bcd ef g

10. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)10 Path Delay and Path Weight  A set of connected nodes specify a path. A path does not traverse through the host node.  Path delay = ∑ d(vi) = combinational delay of path  Path weight = ∑ wij = clock delay of path  Retiming of a node i is denoted by an integer ri  It represents the number of registers moved across, initially ri = 0  Register moved from output to input, ri → ri + 1  Register moved from input to output, ri → ri – 1  After retiming, edge weight wij’ = wij + rj – ri

11. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)11 Example of Node Retiming 3 3 3 3 3 3 ∑ d(vi) = 12, ∑ wij = 0 3 3 3 3 3 3 ∑ d(vi) = 12, ∑ wij = 2 r1 = 0 r2 = 0r3 = 0 r4 = 0 r5 = 0 r6 =0 r1 = 0 r2 = -1r3 = 0 r4 = 0 r5 = 1 r6 =0

12. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)12 Legal Retiming  Retiming is legal if the retimed circuit has no negative weights.  A legally retimed circuit is functionally equivalent to the original circuit – proof by Leiserson and Saxe (1991)  Retiming is the most general method for changing the register count and position without knowing the functions of vertices.

13. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)13 Example FF a b c x d c host x 1 0 0 0

14. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)14 Example: Illegal Retiming c host x 1 0 0 0 0 0 0 Retiming vector = {0, 0, 0} c host x 1 → 0 0 0 → –1 0 →1 0 0 0 → –1 Retiming vector = {0, 0, –1} FF a b c x d

15. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)15 Example: Legal Retiming c host x 1 0 0 0 0 0 0 Retiming vector = {0, 0, 0} c host x 1 → 0 0 0 0 →1 0 0 Retiming vector = {0, 1, 0} FF a b c x d

16. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)16 Correlator Circuit 777 3333 0 0 0 0 0 0 0 0 1 11 1 a b c d e f g h Initial retiming vector = {0,0,0,0,0,0,0,0} Critical path delay = 24 rh=0 ra=0 rb=0rc=0 rd=0 re=0 rf=0 rg=0

17. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)17 Retimed Correlator Circuit 777 3333 0 0 0→1 0 0 0 1→0 1 1 a b c d e f g h retiming vector = {-1,-1,-2,-2,-2,-1,0,0} Critical path delay = 13 rh=0 ra= -1 rb= -1rc= -2 rd= -2 re= -2 rf= -1 rg=0

18. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)18 Retiming Theorem  Given a network G(V, E, W) and a cycle time T, (r1,... ) is a feasible retiming if and only if: 1. ri – rj ≤ wijfor all edges (vi,vj) ε E 2. ri – rj ≤ W(vi,vj) – 1 for all node-pairs vi, vj such that D(vi,vj) > T Where, W(vi,vj):is the minimum weight for all paths between vi and vj D(vi,vj):is the maximum delay among all minimum weight paths between vi and vj

19. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)19 Proof of Condition 1  We assume that the original network is legal, i.e., all edge weights are positive.  For an arbitrary edge (vi,vj) ε E: ri – rj ≤ wij or wij + rj – ri ≥ 0, means that after retiming the new weight wij’ = wij + rj – ri will be positive. Thus, condition 1 ensures the legality of retiming.

20. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)20 Proof of Condition 2  Given: d(vi) < T, for all i.  Any retimed path whose combinational delay exceeds clock period, will have at least one flip-flop.  The above is the requirement for correct operation. i j Original weight, Wij Retimed weight, Wij’ = Wij + rj – ri ≥ 1 Path (i,j), D(i,j) > T Wij flip-flops rj flip-flops ri flip-flops

21. Spring 08, Feb 28ELEC 7770: Advanced VLSI Design (Agrawal)21 References  Two papers by Leiserson et al. (see slide 2).  G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994.  N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Boston: Springer, 1999.