2. t Popularity of the Internet t Provides universal interconnection between individual groups that use different hardware suited for their needs t Based on IP protocol which : 4 doesn’t depend on hardware 4 address architecture enables subnetting 4 a lot of applications and software are based on IP protocol 6 Routing is implemented by software

3. t High speed network t Optical fibers are used as infrastructure t All packets are of fixed length called cells t Routing of the packets is done in hardware t Integration of multiple wide bandwidth traffic types 6 Transfer of the IP datagrams over ATM needs additional software for encapsulation

4. t Based on IP Protocol : 4 physical IP addressing 4 network packets - IP datagrams t High speed network : 4 routing is done in HARDWARE 4 traffic is implemented by optical fibers 4 switching of wide bandwidth data is allowed

5. t To build the entire NIP network 4 different projects are being designed in the lab at the same time: 4 native IP switch 4 program for switch management 4 network card for host computers connected to Native IP 4 network card IP/ATM for direct support of routing IP datagramms over ATM network.

6. The Banyan Switch The Shared Memory Switch

7. Memory Block PCI9080 155 Mbps Control Unit Memory BUS Port Interface III 155 Mbps Memory Control BUS Port Interface II Port Interface I 155 Mbps Port Interface III 155 Mbps Port Interface II Port Interface I Routing table

8. PHY 8bit 155bps 8=>64 sod eod Memory bus 8<=64 sod eod 8bit 64 bits request wait

9. Packet A Packet B Empty Packet B Packet A Packet B 127 0 1 2 3 126

10. BUS Arbitration state machine requests waits Page Control Table Routing Table PLX9080 Control & Memory Address Local bus Page Handler Memory Controller WERE PCI bus PHI Configuration Registers Switch Configuration Registers Switch Status Registers Page Link Table

11. t Every port can read from the memory one time in 8 cycles (if he asks to) t Every port can write to the memory one time in 8 cycles (if he asks to) t The port connected to computer can read more frequently First is writing First is reading Second is writing Second is reading Third is writing Third is reading

12. MaskIP Address Destination 31 0030 There are 25 entries in the table

13. Link Table Control Table 2 10 32 126 2 10 Empty 012345615 Not usedPage is Full Last Page Port IDLast Entry OffsetFull Datagram filled 4 pages: in order 32, 126, 2, 10

14. Empty pages fifo I channel fifo II channel fifo III channel fifo IV channel fifo I II III IV I II III IV Arbitration logic Memory Address Bus Control Signals from Port Interfaces Control Signals from Port Interfaces

15. t Fully IP compatible t Supports subnetting t Supports multicasting t Connection to the computer is through PCI BUS t Routing is done according to the routing table that is updated from the computer t Computer is responsible to route every packet which address is not mentioned in the table - optional

16. t Performs all switching functions t Has 4 155Mbps ports : 4 3 of them can be hosts or another switches 4 fourth is connected to the computer and can operate at up to 4x155Mbps rate through DMA device t Switch has 3 standard PHY interface devices(standard UTOPIA interface to the PHY module) t Output port contention is resolved by means of store-and-forward buffering

17. t Has status register: 4 status of each port 4 instantaneous switch status 4 main memory status t Has control register: 4 is set by computer 4 basic functionality mode