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CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 1 trend toward higher levels of integration Evolution of Implementation Technologies zDiscrete devices:

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Presentation on theme: "CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 1 trend toward higher levels of integration Evolution of Implementation Technologies zDiscrete devices:"— Presentation transcript:

1 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 1 trend toward higher levels of integration Evolution of Implementation Technologies zDiscrete devices: relays, transistors (1940s-50s) zDiscrete logic gates (1950s-60s) zIntegrated circuits (1960s-70s) ye.g. TTL packages: Data Book for 100’s of different parts yMap your circuit to the Data Book parts zGate Arrays (IBM 1970s) y“Custom” integrated circuit chips yDesign using a library (like TTL) yTransistors are already on the chip yPlace and route software puts the chip together automatically y+ Large circuits on a chip y+ Automatic design tools (no tedious custom layout) y- Only good if you want 1000’s of parts

2 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 2 Gate Array Technology (IBM - 1970s) zSimple logic gates yUse transistors to implement combinational and sequential logic zInterconnect yWires to connect inputs and outputs to logic blocks zI/O blocks ySpecial blocks at periphery for external connections zAdd wires to make connections yDone when chip is fabed x“mask-programmable” yConstruct any circuit

3 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 3 Programmable Logic zDisadvantages of the Data Book method yConstrained to parts in the Data Book yParts are necessarily small and standard yNeed to stock many different parts zProgrammable logic yUse a single chip (or a small number of chips) yProgram it for the circuit you want yNo reason for the circuit to be small

4 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 4 Programmable Logic Technologies zFuse and anti-fuse yFuse makes or breaks link between two wires yTypical connections are 50-300 ohm yOne-time programmable (testing before programming?) yVery high density zEPROM and EEPROM yHigh power consumption yTypical connections are 2K-4K ohm yFairly high density zRAM-based yMemory bit controls a switch that connects/disconnects two wires yTypical connections are.5K-1K ohm yCan be programmed and re-programmed in the circuit yLow density

5 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 5 Programmable Logic zProgram a connection yConnect two wires ySet a bit to 0 or 1 zRegular structures for two-level logic (1960s-70s) yAll rely on two-level logic minimization yPROM connections - permanent yEPROM connections - erase with UV light yEEPROM connections - erase electrically yPROMs xProgram connections in the _____________ plane yPLAs xProgram the connections in the ____________ plane yPALs xProgram the connections in the ____________ plane

6 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 6 PAL Logic Building Block zProgrammable AND gates zFixed OR/NOR gate zFlipflop/Registered Output zFeedback to Array zTri-state Output

7 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 7 XOR PALs zUseful for comparator logic, arithmetic sums, etc. yUse of XOR gates can dramatically reduce the number of AND plane inputs needed to realize certain functions

8 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 8 XOR PAL zAnd/Or/XOR Logic zFeedback zRegistered Outputs zTri-State Outputs

9 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 9 Another Variation: Synchronous vs. Asynchronous Outputs

10 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 10 Making Large Programmable Logic Circuits zAlternative 1 : “CPLD” yPut a lot of PLDS on a chip yAdd wires between them whose connections can be programmed yUse fuse/EEPROM technology zAlternative 2: “FPGA” yEmulate gate array technology yHence Field Programmable Gate Array yYou need: xA way to implement logic gates xA way to connect them together

11 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 11 Field-Programmable Gate Arrays zPALs, PLAs = 10s – 100s Gate Equivalents zField Programmable Gate Arrays = FPGAs yAltera MAX Family yActel Programmable Gate Array yXilinx Logical Cell Array z1000s - 100000(s) of Gate Equivalents!

12 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 12 Field-Programmable Gate Arrays zLogic blocks yTo implement combinational and sequential logic zInterconnect yWires to connect inputs and outputs to logic blocks zI/O blocks ySpecial logic blocks at periphery of device for external connections zKey questions: yHow to make logic blocks programmable? yHow to connect the wires? yAfter the chip has been fabbed

13 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 13 Tradeoffs in FPGAs zLogic block - how are functions implemented: fixed functions (manipulate inputs) or programmable? ySupport complex functions, need fewer blocks, but they are bigger so less of them on chip ySupport simple functions, need more blocks, but they are smaller so more of them on chip zInterconnect yHow are logic blocks arranged? yHow many wires will be needed between them? yAre wires evenly distributed across chip? yProgrammability slows wires down – are some wires specialized to long distances? yHow many inputs/outputs must be routed to/from each logic block? yWhat utilization are we willing to accept? 50%? 20%? 90%?

14 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 14 8 Product Term AND-OR Array + Programmable MUX's Programmable polarity I/O Pin Seq. Logic Block Programmable feedback Altera EPLD (Erasable Programmable Logic Devices) zHistorical Perspective yPALs: same technology as programmed once bipolar PROM yEPLDs: CMOS erasable programmable ROM (EPROM) erased by UV light zAltera building block = MACROCELL

15 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 15 Altera EPLDs contain 10s-100s of independently programmed macrocells Personalized by EPROM bits: Flipflop controlled by global clock signal local signal computes output enable Flipflop controlled by locally generated clock signal + Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear function Altera EPLD: Synchronous vs. Asynchronous Mode

16 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 16 AND-OR structures are relatively limited Cannot share signals/product terms among macrocells Logic Array Blocks (similar to macrocells) Global Routing: Programmable Interconnect Array 8 Fixed Inputs 52 I/O Pins 8 LABs 16 Macrocells/LAB 32 Expanders/LAB EPM5128: Altera Multiple Array Matrix (MAX)

17 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 17 LAB Architecture Expander Terms shared among all macrocells within the LAB Efficient way to use AND plane resources Macrocell ARRAY I/O Block Expander Product Term ARRAY I N P U T S P I A I/O Pad

18 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 18 Supports large number of product terms per output Latches and muxes associated with output pins P22V10 PAL

19 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 19 Rows of programmable logic building blocks + rows of interconnect Anti-fuse Technology: Program Once 8 input, single output combinational logic blocks FFs constructed from discrete cross coupled gates Use Anti-fuses to build up long wiring runs from short segments Actel Programmable Gate Arrays

20 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 20 Basic Module is a Modified 4:1 Multiplexer Example: Implementation of S-R Latch Actel Logic Module

21 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 21 Interconnection Fabric Actel Interconnect

22 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 22 Jogs cross an anti-fuse minimize the # of jogs for speed critical circuits 2 - 3 hops for most interconnections Actel Routing Example

23 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 23 Actel’s Next Generation: Axcelerator zC-Cell yBasic multiplexer logic plus more inputs and support for fast carry calculation yCarry connections are “direct” and do not require propagation through the programmable interconnect

24 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 24 Actel’s Next Generation: Accelerator zR-Cell yCore is D flip-flop yMuxes for altering the clock and selecting an input yFeed back path for current value of the flip-flop for simple hold yDirect connection from one C- cell output of logic module to an R-cell input; Eliminates need to use the programmable interconnect zInterconnection Fabric yPartitioned wires ySpecial long wires

25 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 25 Xilinx Programmable Gate Arrays zCLB - Configurable Logic Block y5-input, 1 output function yor 2 4-input, 1 output functions yoptional register on outputs zBuilt-in fast carry logic zCan be used as memory zThree types of routing ydirect ygeneral-purpose ylong lines of various lengths zRAM-programmable ycan be reconfigured

26 Programmable Interconnect I/O Blocks (IOBs) Configurable Logic Blocks (CLBs)

27 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 27 The Xilinx 4000 CLB

28 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 28 Two 4-input functions, registered output

29 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 29 5-input function, combinational output

30 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 30 CLB Used as RAM

31 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 31 Fast Carry Logic

32 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 32 Xilinx 4000 Interconnect

33 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 33 Switch Matrix

34 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 34 Xilinx 4000 Interconnect Details

35 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 35 Global Signals - Clock, Reset, Control

36 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 36 Xilinx 4000 IOB

37 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 37 Xilinx FPGA Combinational Logic Examples zKey: General functions are limited to 5 inputs y(4 even better - 1/2 CLB) yNo limitation on function complexity zExample  2-bit comparator: A B = C D and A B > C D implemented with 1 CLB (GT)F = A C' + A B D' + B C' D' (EQ)G = A'B'C'D'+ A'B C'D + A B'C D'+ A B C D zCan implement some functions of > 5 input

38 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 38 CLB 5-input Majority Circuit CLB 7-input Majority Circuit Xilinx FPGA Combinational Logic zExamples yN-input majority function: 1 whenever n/2 or more inputs are 1 yN-input parity functions: 5 input/1 CLB; 2 levels yield 25 inputs! CLB 9 Input Parity Logic

39 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 39 Xilinx FPGA Adder Example zExample y2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, Cout Full Adder, 4 CLB delays to final carry out 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out

40 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 40 Xilinx Vertex-II Family z88-1000+ pins z64-10000+ CLBs yCombinational and sequential logic using lookup tables and flip-flops yRandom-access memory yShift registers for use as buffer storage zMultipliers regularly placed throughout the CLB array to accelerate digital signal processing applications zE.g., the XC2V8000: 11,648 CLBs, 1108 IOBs, 90,000+ FFs, 3Mbits RAM (168 x 18Kbit blocks), 168 multipliers yEquivalent to eight million two-input gates!

41 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 41 Xilinx Vertex-II Family IOB zTri-state/bidirectional driver zRegisters for each of three signals involved: input, output, tri-state enable. zTwo registers to latch values with separate clocks. zFor large pinouts, separate clocks stagger signals changes to avoid large current spikes zFFs used for synchronization as well as latching

42 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 42 Xilinx Vertex-II Family CLB zFour basic slices in two groups zEach has a fast carry-chain zLocal interconnect to wire logic of each slice and connect to the CLB array: switch matrix is large collection of programmable switches

43 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 43 Xilinx Vertex-II Family CLB Internals zJust ½ of one slice! z4-input LUT + FF zFast carry logic zMany programmable interconnections for sync vs. async operation

44 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 44 Xilinx Vertex-II Family Fast Carry Logic LUT ABAB ABAB Mux 0 1 Mux 0 1 Ci Co 0 (A  B)Ci (A  B) (A  B  Ci) (A  B)Ci+AB AB 1 A C B 1111 1

45 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 45 Xilinx Vertex-II Family CLB zSequential Portion yTwo positive edge-triggered flip-flops yTransparent latches or flip- flops yAsynchronous or synchronous sets and resets yInitialize to different values at power-up yClocks and load enables complemented or not

46 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 46 Xilinx Vertex-II Family Slice Personality z4-input function generator zOR 16 bits of dual-ported random-access memory (with separate address inputs for read - G1 to G4 - and write - WG1 to WG4) zOR a 16-bit variable-tap shift register zWith muxes, CLB can implement any function of 8 inputs and some functions of 9 inputs zRegistered and unregistered versions of function block outputs

47 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 47 Xilinx Vertex-II Family Interconnections zMethods of interconnecting CLBs and IOBs: (1) direct fast connections within a CLB (2) direct-connections between adjacent CLBs (3) double-lines to fanout signals to CLBs one or two away (4) hex lines to connect to CLBs three or six away (5) long lines that span the entire chip zFast access to neighbors vertically and horizontally with direct connections zDouble and hex lines provide a slightly larger range zLong lines saved for time- critical signals w/ min signal skew

48 CS 150 – Fall 2005 - Lec #27: FPGA Evolution – 48 Programmable Logic Summary zDiscrete Gates zPackaged Logic zPLAs zEver more general architectures of programmable combinational + sequential logic and interconnect yAltera yActel yXilinx—4000 series to Vertex xCLBs implementing logic function generators, RAMs, Shift registers, fast carry logic xLocal, inter-CLB, and long line interconnections

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