1. 048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion isaac@ee.technion.ac.il http://comnet.technion.ac.il/~isaac/ Input-Queued Switches and Head-of-Line Blocking

2. Spring 2006048866 – Packet Switch Architectures2 Where We Are  We have studied output-queued and shared- memory switches  Why they provide an ideal performance (work- conserving)  Why they can hardly be implemented (speed-up)  We have studied performance criteria  Fairness  Queue size  We have studied tools for their analysis  Deterministic  Statistical

3. Spring 2006048866 – Packet Switch Architectures3 Where We Are  We will now study input-queued switches  Why they solve the speed-up problem  A first problem: head-of-line blocking reduces throughput Solution: virtual output queues  A second problem: arbitration between virtual output queues Solution: scheduling algorithms

4. Spring 2006048866 – Packet Switch Architectures4 Outline 1. Head-of-Line Blocking 2. HoL Blocking in Small Switches 3. 58% Throughput

5. Spring 2006048866 – Packet Switch Architectures5 Packets are queued at the inputs. Input-Queued Switch: How It Works The switch matches inputs and outputs…

6. Spring 2006048866 – Packet Switch Architectures6 Input-Queued Switch: How It Works

7. Spring 2006048866 – Packet Switch Architectures7 Input-Queued Switch: Speed-Up Advantage At most one packet leaves from each input (arrives to each output)  speed-up=1, not N

8. Spring 2006048866 – Packet Switch Architectures8 Head-of-Line Blocking Blocked! The switch is NOT work-conserving!

9. Spring 2006048866 – Packet Switch Architectures9 Glimpse: Virtual Output Queues

10. Spring 2006048866 – Packet Switch Architectures10 Outline 1. Head-of-Line Blocking 2. HoL Blocking in Small Switches 3. 58% Throughput

11. Spring 2006048866 – Packet Switch Architectures11 Assumptions  As in analysis of OQ switch:  Time is slotted  At each time-slot, at each of the N inputs: Bernoulli IID packet arrivals with probability   Each packet is destined for one of the N outputs uniformly at random  By symmetry, consider some given output  Scheduling: at each time-slot the output picks an HoL u.a.r. What throughput  can we get?

12. Spring 2006048866 – Packet Switch Architectures12 HoL Blocking in 2x2 Switch

13. Spring 2006048866 – Packet Switch Architectures13 HoL Blocking in 2x2 Switch

14. Spring 2006048866 – Packet Switch Architectures14 HoL Blocking in 2x2 Switch

15. Spring 2006048866 – Packet Switch Architectures15 Balls-and-Bins Model

16. Spring 2006048866 – Packet Switch Architectures16 Balls-and-Bins Model

17. Spring 2006048866 – Packet Switch Architectures17 Balls-and-Bins Model

18. Spring 2006048866 – Packet Switch Architectures18 Balls-and-Bins Model  Saturated switch  Assume infinite number of packets in each queue  They are all destined to some output u.a.r. (random coloring of packets)  Balls-and-bins model  N outputs  N bins  N HoL packets  N balls  At each time-slot 1. Remove one ball from each non-empty bin 2. Assign free balls to bins independently and u.a.r.

19. Spring 2006048866 – Packet Switch Architectures19 Markov Chain  There are three states for the bin occupancy: (2,0), (1,1), (0,2)  E.g., (2,0) means both HoL packets are destined to first output  We get a Markov chain: (2,0)(1,1)(0,2)

20. Spring 2006048866 – Packet Switch Architectures20 Transition Probabilities in Markov Chain 1/2  Transition from (2,0)

21. Spring 2006048866 – Packet Switch Architectures21 Transition Probabilities in Markov Chain (2,0)(1,1)(0,2) 1/2 1/4  Equilibrium state distribution:  ={¼, ½, ¼}  Output throughput=1-P(output empty) =75%

22. Spring 2006048866 – Packet Switch Architectures22 Side Note: State Collapse (2,0)(1,1) 1/2  Symmetric Markov chain  State collapse: (2,0) and (1,1)  Equilibrium (collapsed) state distribution: (1/2,1/2)  get real state distribution

23. Spring 2006048866 – Packet Switch Architectures23 3x3 Switch  Markov chain with following states: (3,0,0),(0,3,0),(0,0,3), (2,1,0),(2,0,1),(1,2,0),(0,2,1),(0,1,2),(1,0,2) (1,1,1)  State collapse into: (3,0,0),(2,1,0) and (1,1,1) (3,0,0)(2,1,0)(1,1,1) 1/3 2/3 2/9 1/9

24. Spring 2006048866 – Packet Switch Architectures24 3x3 Switch  Equilibrium state distribution  Per-output throughput  75% for 2x2, 68% for 3x3… but state space explosion for large N

25. Spring 2006048866 – Packet Switch Architectures25 Outline 1. Head-of-Line Blocking 2. HoL Blocking in Small Switches 3. 58% Throughput

26. Spring 2006048866 – Packet Switch Architectures26 Method #2: Recurrence Equations  Consider a given bin (output)  Let X t be the number of balls in this bin  Number of HoL packets for this output  Let A t be the number of arrivals to this bin  Let B t be the number of departures from all bins  The recurrence equation is:

27. Spring 2006048866 – Packet Switch Architectures27 Method #2: Recurrence Equations  The only queues with new HoL packets are those from which HoL packets left at the last time-slot  A t+1 is the sum of B t Bernoulli I.I.D. variables:

28. Spring 2006048866 – Packet Switch Architectures28 Method #2: Recurrence Equations  Steady-state: E[B] is N times the per- output throughput  As N ! 1, binomial goes to Poisson and (N  x (1/N) !  (approximation)

29. Spring 2006048866 – Packet Switch Architectures29 Method #2: Recurrence Equations  Same equations lead to same results (cf OQ switch)  When switch is saturated, there are N balls for N bins: EX=1  Hence

30. Spring 2006048866 – Packet Switch Architectures30 OQ switch HoL Blocking vs. OQ Switch IQ switch with HoL blocking