1. CSCI 660 EEGN-CSCI 660 Introduction to VLSI Design Lecture 6 Khurram Kazi

2. CSCI 660 2 Introduction to Verilog  Present day ASIC/FPGA designers most likely have to work with VHDL and Verilog in one form or another.  People who used VHDL mostly, are likely to encounter Verilog as the language that describes the gate level netlist.  Good to know both HDLs.  Both have their strong points and have weaknesses.

3. CSCI 660 3 Verilog Vs VHDL  Verilog is perceived to be loosely typed language.  VHDL strongly typed language.  Fact of the matter is that ones choice of VHDL over Verilog or vice versa most likely tends to be based ones familiarity with either of the languages or company’s past history of development platform.  Both languages serve as an excellent tool for RTL development.  Neither of them is well suited for the verification of complex ASICs especially that are algorithmic intensive.  Languages like specman ‘e’, Synopsys “vera”, SystemC, System Verilog or C/C++ have become the languages of choice for verification platform.

4. CSCI 660 4 Syntax used in describing a module Module is a fundamental block in Verilog that is synonymous to entity. Verilog does not support different architectures for the same entity module (port list); endmodule

5. CSCI 660 5 Continuous assignment This is synonymous to concurrent block statement in VHDL // get continuously updated whenever any of the input operands // change value. module new_or ( a, b, c, ); input a; input b; output c; assign c = (a | | b); // OR function is implied here endmodule

6. CSCI 660 6 Initial block // Initial block consists of a statement or a group of statements enclosed in a begin and // end which will be executed only once at simulation time 0. If there is more than one // initial block they get executed concurrently independent of each other. Normally used // for initializing, monitoring, generating clocks etc. module stimulus1 initial reset_n = 1’b0; #25 reset_n = 1’b1; end; initial begin // multiple statements have to be lumped together variable1 = 0; #10 variable1 = 1; #10 variable1 = 0 #30 variable1 = 1; #50 variable1 = 0; end;

7. CSCI 660 7 Always block // statements in the “always” block repeatedly get executed until the simulation is // stopped by $finish or $stop. Similar to a process in VHDL // Block that generates a clock module clk_gen reg clk; Intial begin clk = 1’b0; // setting the initial value of the clock end always begin #25 clk = ~clk; // clock repeating every 50 time units end Intial begin #5000 $finish; // simulation ends after 5000 time units end endmodule clk_gen

8. CSCI 660 8 Module instantiation (by position) module couple_of_ands ( a, b, c, d ); input a; input b; input c; output d wire w1; // two instances of the module testands testands and1 (a, b, w1); // assuming the 1 st two ports are inputs and 3 rd // is the output of the and gate testands and2 (w1, c, d); endmodule

9. CSCI 660 9 Module instantiation (connectivity by name) module mux4cbn ( out, a, b, sel ); output [3:0] out; input [3:0] a, b; input sel; // the inputs and output of the mux2 are 2 bits wide Mux2hi (.a(a[3:2]),.b(b[3:2]),.sel(sel),.out(out3:2]) ); Mux2lo (.a(a[1:0]),.b(b[1:0]),.out([out3:2]),.sel(sel) ); endmodule Name of net being connected.portname(net_to_be_connected) Name of port in lower level module (period indicating a hierarchical name)

10. CSCI 660 10 Data Objects  Nets represent connections between hardware elements. They are one-bit values by default unless they are declared explicitly as vectors. Term wire and net are often used interchangeably.  Net is not a keyword but represents a class of data types such as wire, wand, wor, tri, triand, trior, trireg, etc.  Nets/wires are most common data objects to interconnect modules. The default net type is a plain wire. There are wired OR, wired AND, pullups, pulldowns etc.  For synthesis use wire only!! wire a, b, c; // three 1-bit nets of type wire wire [7:0] d, e, f; // three 8-bit vectors Verilog implicitly declares nets for every port declaration. Every connection made in a module instance or primitive instance is also implicitly declared as a net, if it isn’t already declared. Nets get the output value of their drivers. If net has no driver, it gets the value z

11. CSCI 660 11 Registers  Registers represent data storage elements. Register retain value until another value is placed onto them.  The register (reg) data object holds its value from one procedural assignment statement to the next and holds its value from one to the next simulation cycle.  It DOES NOT imply that a physical register will be synthesized.  The fundamental difference between nets and registers is that the registers have to be assigned values explicitly. Once a value is assigned to a register, it is held until next procedural assignment to it.  Verilog registers do not need a clock as hardware registers. Same word different meaning (all in the context)  Values of registers can be changed anytime in a simulation by assigning a new values to the register

12. CSCI 660 12 Port Connection Rules when modules are instantiated  Inputs: Internally, input ports must always be of type net. Externally, the inputs can be connected to a variable which is a reg or a net.  Output: Internally, output ports can be of the type reg or net. Externally, outputs must always be connected to a net. They cannot be connected to a reg.  Inouts: Internally, inout ports must always be of the type net. Externally, inout ports must always be connected to a net. Outside the module: Inputs can be Reg or net Inside the module: Input port must always be net only Inside the module: Output ports can be of net or reg type Outside the module: Outputs must always be connected to nets Inside the module: Inout ports: net only inside Outside the module: inout: net only outside

13. CSCI 660 13 Numbers Number of bits ‘ radixValue ‘b ‘B Binary ‘d ‘D Decimal ‘h ‘H Hexadecimal ‘o ‘O Octal 8’b10010001 8’d245

14. CSCI 660 14 Description of a flip flop module fflop (q, data, reset_n, clk); output q; input data, reset_n, clk; reg q; //Output port q holds value; Therefore, it is declared as reg. always @(posedge clk) if (reset_n == 0) // this can also be written as “if (!reset_n)” q = 1’b0; else q = data; endmodule // fflop

15. CSCI 660 15 Description of a flip flop with asynchronous reset_n module fflop_async (q, data, reset_n, clk); output q; input data, reset_n, clk; reg q; always @(posedge clk or negedge reset_n) if (!reset_n) q = 1’b0; else q = data; endmodule // fflop_async ** Since the clk is not used in any conditional statement, hence implicitly the synthesis tool knows that clk is the CLOCK signal

16. CSCI 660 16 Arithmetic operators  Binary: +, -, *, /, % (the modulus operator)  Unary: +, - (e.g. -4 represents Negative 4; +5 represents Positive 5)  Integer division truncates any fractional part  The result of a modulus operation takes the sign of the first operand  If any operand bit value is the unknown value x, then the entire result value is x  Register data types are used as unsigned values  negative numbers are stored in two ’ s complement form

17. CSCI 660 17 Relational Operators  a<b a less than b  a>b a greater than b  a<=b a less than or equal to b  a>=b a greater than or equal to b  The result is a scalar value:  0 if the relation is false  1 if the relation is true  x results if any of the operands has unknown x bits  Note: If a value is x or z, then the result of that test is false

18. CSCI 660 18 Equality Operators  a === ba equal to b, including x and z  a !== ba not equal to b, including x and z  a == ba equal to b, result may be unknown  a != ba not equal to b, result may be unknown  Operands are compared bit by bit, with zero filling if the two operands do not have the same length  Result is 0 (false) or 1 (true)  For the == and != operators the result is x, if either operand contains an x or a z  For the === and !== operators  bits with x and z are included in the comparison and must match for the result to be true  the result is always 0 or 1

19. CSCI 660 19 Logical Operators  Logical operators always evaluate to a 1-bit value, 0 (false), 1 (true), or x (ambiguous)  If an operand is not equal to zero, it is equivalent to a logical 1 (true condition). If it is equal zero, it is equivalent to a logical 0 (false condition). If an operand bit is x or z, it is equivalent to x (ambiguous condition and is normally treated by the simulator as a false condition  E.g. A = 3; B = 0;  ! logic negation!A //Evaluates to 0  && logical and A && B //Evaluates to 0  || logical orA || B // Evaluates to 1  Expressions connected by && and || are evaluated from left to right  Evaluation stops as soon as the result is known  The result is a scalar value:  0 if the relation is false  1 if the relation is true  x if any of the operands has unknown x bits

20. CSCI 660 20 Bit-wise operators  ~ negation  & and  | inclusive or  ^ exclusive or  ^~ or ~^ exclusive nor (equivalence)  Computations include unknown bits, in the following way:  ~x = x  0&x = 0  1&x = x&x = x  1|x = 1  0|x = x|x = x  0^x = 1^x = x^x = x  0^~x = 1^~x = x^~x = x  When operands are of unequal bit length, the shorter operand is zero-filled in the most significant bit positions

21. CSCI 660 21 if -- else if -- else syntax

22. CSCI 660 22 case statement

23. CSCI 660 23 for loop synthesis integer i; always @ (a or b) begin for (i = 0; i < 6; i = i + 1) example[i] = a[i] & b [5 – i]; end Example(0) <= a(0) and b(5); Example(1) <= a(1) and b(4); Example(2) <= a(2) and b(3); Example(3) <= a(3) and b(2); Example(4) <= a(4) and b(1); Example(5) <= a(5) and b(0); for loops are “unrolled” and then synthesized.

24. CSCI 660 24 Basic Verilog file // Use two slashes for comments module simple_counter ( reset_n, sys_clk, enable, count8 ); //end port list // Input ports declaration input reset_n; input sys_clk; input enable; // Output ports\par output [3:0] count8; // Input ports Data Type // By rule all the input ports should be wires wire sys_clk; //by default they are and dont wire reset_n; // need to specify as wire wire enable; // Output ports data type // Output ports can be storage elements or a wire reg [3:0] count8; //Code start // Counter uses +ve edge triggered and // has synchronous reset_n always @ (posedge sys_clk) begin : COUNT // Block Name if (reset_n == 1'b0) begin count8 <= 4'b000; end // Counter counts when enable is 1 else if (enable == 1'b1) begin count8 <= count8 + 1; end end // end of block COUNT endmodule // end of module // simple_counter

25. CSCI 660 25 Basic Verilog file: testbench portion // // Copyright 2006 Mentor Graphics Corporation // // All Rights Reserved. // // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF // MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. // module test_counter; reg clk, reset, enable; wire [3:0] count; simple_counter dut (.reset_n(reset),.enable(enable),.count8(count),.sys_clk(clk)); initial // Clock generator begin clk = 0; forever #10 clk = !clk; end initial// Test stimulus begin reset = 0; enable = 0; #20 reset = 1; #20 enable = 1; end endmodule

26. CSCI 660 26 ModelSim command to run Verilog simulations vsim –voptargs=+acc design_name Where design_name is the top level entity name that you are trying to simulate!!