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An Efficient Hardware-based Multi-hash Scheme for High Speed IP Lookup Department of Computer Science and Information Engineering National Cheng Kung University,

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Presentation on theme: "An Efficient Hardware-based Multi-hash Scheme for High Speed IP Lookup Department of Computer Science and Information Engineering National Cheng Kung University,"— Presentation transcript:

1 An Efficient Hardware-based Multi-hash Scheme for High Speed IP Lookup Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C. Authors: Socrates Demetriades, Michel Hanna, Sangyeun Cho and Rami Melhem Publisher: High Performance Interconnects, 2008. HOTI '08. 16th IEEE Symposium on 26-28 Aug. 2008 Present: Chia-Ming,Chuang Date: 9, 24, 2008

2 Outline 1. Introduction 2. Architecture 3. Bit select mechanism 4. Conclusion

3 Introduction (1/3) Ternary Content Addressable Memory (TCAM) Trie-based schemes Hash-based schemes Current techniques IP lookup have three categories

4 Introduction (2/3) First hashing can happen collisions and requires resolution techniques that may result in unpredictable lookup performance Second hash keys be included “don’t care” bit Three determine the longest prefix hash-based IP lookup problem

5 Introduction (3/3) High lookup throughput A multiple table, multiple hash functions Bit select mechanism high space utilization Modified version of the Cuckoo hashing algorithm Low power consumption Sum of advantage

6 Outline 1. Introduction 2. Architecture 3. Bit select mechanism 4. Conclusion

7 Architecture overview (1/4)

8 Architecture (2/4) Based on a multi-level hash table (MHT) All hash function use the same bit position in a prefix or a destination address PS:references [16] S. Cho, J. Martin, R. Xu, M. Hammoud, and R. Melhem, “Ca-ram: A high-performance memory substrate for search-intensive applications,” pp. 230–241, IEEE ISPASS, April 2007.

9 Architecture (3/4)

10 Architecture (4/4) Do not classify prefixes based on their lengths Each table is accessed using a hardware based index generator a number of match processors compare the fetched keys with the search key in parallel “Bit-Select” component (1)decides which bits participate in the index generation (2)“don’t care bits” may appear in the selected bits for indexing (3)Bit-Select mechanism needs to resolve this by prefix expansion

11 Outline 1. Introduction 2. Architecture 3. Bit select mechanism 4. Conclusion

12 Bit select mechanism (1/7)

13 Bit select mechanism (2/7) ( 一 ) Most prefix have lenghts between16 and 24 bits 24 bit prefixes comprise about 54% no prefixes less than 8 bit ( 二 ) As a study in [9] pointed out, regardless of prefix length, start from the6th bit and reach the prefixes’ maximum length.

14 Bit select mechanism (3/7)

15 15 Bit select mechanism (4/7) ( 一 ) X-axis =>(Expansion size)/extra provided capacity Y-axis=> unresolved collisions no prefixes less than 8 bit ( 二 ) From the experiments, we find that any configuration that can keep the expansion between 20% and 90% of the extra provided capacity results in less than 5% of unresolved collisions.

16 Bit select mechanism (5/7) controlled prefix expansion controlled wildcard resolution

17 17 Max bucket is 234 item Max bucket is 49 item Total 49*3=147 Cuckoo hashing algorithm Bit select mechanism (6/7)

18 18 Bit select mechanism (7/7) ( 一 ) a collision may appear if an item x can not be inserted into tables Ti, i = 1,..., d because buckets Ti [hi(x)], i = 1,..., d are full. ( 二 ) by checking whether an item y at some bucket Ti [hi(x)], 1 ≤ i ≤ d, can migrate to some other table Tj =\ Ti. This requires that a bucket Tj [hj(y)] has an empty entry to accommodate the item y. ( 三 ) If such an item y is found, then it can be moved and x will take its place.

19 Outline 1. Introduction 2. Architecture 3. Bit select mechanism 4. Conclusion

20 Conclusion (1/3)

21 Conclusion (2/3)

22 Conclusion (3/3)


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