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1 CS 201 Makefile Debzani Deb. 2 Remember this? 3 What is a Makefile? A Makefile is a collection of instructions that is used to compile your program.

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Presentation on theme: "1 CS 201 Makefile Debzani Deb. 2 Remember this? 3 What is a Makefile? A Makefile is a collection of instructions that is used to compile your program."— Presentation transcript:

1 1 CS 201 Makefile Debzani Deb

2 2 Remember this?

3 3 What is a Makefile? A Makefile is a collection of instructions that is used to compile your program. –"make" is a program that looks for a file called "makefile" or "Makefile“ and executes the instructions in it. Makefiles are very helpful when dealing with projects (having many source files). –Once you modify some source files in your project, and type the command "make“, your program will be recompiled using as few compilation commands as possible.

4 4 A Typical Makefile Whenever, “make” command is issued in the command prompt, this file is executed. The filename must be Makefile # Makefile for hello.c # Debzani Deb, CS 201 # hello: hello.o gcc -o hello hello.o hello.o: hello.c gcc -c hello.c hello.c hello.o hello Source file Object file Executable file

5 5 A Typical Makefile # Makefile for hello.c # Debzani Deb, CS 201 # hello: hello.o gcc -o hello hello.o hello.o: hello.c gcc -c hello.c COMMENTS: always starts with #

6 6 A Typical Makefile # Makefile for hello.c # Debzani Deb, CS 201 # hello: hello.o gcc -o hello hello.o hello.o: hello.c gcc -c hello.c DEPENDENCY line Target Target’s Prerequisite RULE line: must starts with a tab  hello  depends on  hello.o , if  hello.o  changes, then hello must be rebuild. And in order to rebuild  hello , the  Rule  below dependency line must be executed.

7 7 DEPENDENCY line A Typical Makefile # Makefile for hello.c # Debzani Deb, CS 201 # hello: hello.o gcc -o hello hello.o hello.o: hello.c gcc -c hello.c Time stamp on the file  hello  is compared to the time stamp of file  hello.o . If the target’s time stamp is earlier than prerequisite’s time stamp, the rule below this dependency line is executed.

8 8 Can you see the similarities? # Makefile for hello.c # Debzani Deb, CS 201 # hello: hello.o gcc -o hello hello.o hello.o: hello.c gcc -c hello.c

9 9 Makefile (Summary) Build a dependency line for every target. Add a rule line to rebuild the target. Start rule line with a tab. Add comments to the top of the file. Save these lines in an ASCII file called Makefile. Makefiles are very powerful. Pretty much anything that needs to be compiled (postscript, java, Fortran), can utilize makefiles.


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