1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 20 - Chip-Level Design Spring 2007

2. ECE 425 Spring 2007Lecture 20 - Chip-Level Design2 Announcements  Reading  Book: 7.1 - 7.4  Where We Are  Last Time: Sequential Logic Storage Elements Sequential Logic Testing  Today Chip-Level Design –Packaging –Pad Design –Floorplanning

3. ECE 425 Spring 2007Lecture 20 - Chip-Level Design3 Overview - Chip-Level Design  Packaging  Pad Design  Floorplanning

4. ECE 425 Spring 2007Lecture 20 - Chip-Level Design4 Chip Packaging  Purposes of Packaging  Protect chip die from damage  Provide connection points to PC board  Conduct heat away from chip  External connection: Pins  Internal connection: Pads  Connections performed by bonding machine

5. ECE 425 Spring 2007Lecture 20 - Chip-Level Design5 Common package types:  Dual-inline package (DIP) *  PLCC  Surface mount  Pin-grid array  Ball-grid array  Flip-chip  Multi-chip modules

6. ECE 425 Spring 2007Lecture 20 - Chip-Level Design6 Some Common Packages DIP PGA PLCC

7. ECE 425 Spring 2007Lecture 20 - Chip-Level Design7 DIP Package  Used in early chips  Not popular today due to size, pin limits  MOSIS chips: 40-pin DIPs

8. ECE 425 Spring 2007Lecture 20 - Chip-Level Design8 Surface-Mount Package  Mechanically mounted on PC board  Smaller than DIPs Graphic Source: MemMan.com

9. ECE 425 Spring 2007Lecture 20 - Chip-Level Design9 Ball Grid Array Detail BGA Graphic Source: Analog Devices, Inc. http://www.analog.com/technology/dsp/EZAnswers/manufacturing/bga/background.html

10. ECE 425 Spring 2007Lecture 20 - Chip-Level Design10 Chip Lead Inductance  Recall inductor voltage  V = L*(di/dt)  Result: voltage spikes when current changes rapidly (like, on a clock edge)  Example (from Wolf book):  L = 0.5 nH;  i L = 1A;  v L = 0.5 V.  Workaround: use multiple Vdd, Gnd pins (Wolf Book: First Pentium had 497 each!)

11. ECE 425 Spring 2007Lecture 20 - Chip-Level Design11 I/O Pads  Pads attach chip to "outside world"  Wires to pins are bonded to pads on top-level metal  Output pads: must drive large loads  Input pads: must protect from ESD (Electrostatic Discharge)  Pad cells - connect to form a pad frame  Pad locations  Common approach: pad frame around periphery of chip  Less common approach: pads across entire chip surface  Some advanced packaging systems bond directly to package without bonding wire

12. ECE 425 Spring 2007Lecture 20 - Chip-Level Design12 Pad Frame Organization

13. ECE 425 Spring 2007Lecture 20 - Chip-Level Design13 Pad Frame Organization  Must supply power/ground to each pad as well as chip core.  Positions of pads around frame may be determined by pinout requirements on package.  Want to distribute power/ground pins as evenly as possible to minimize power distribution problems.

14. ECE 425 Spring 2007Lecture 20 - Chip-Level Design14 Input Pads  Problem: Electrostatic Discharge (ESD) can destroy circuit  high voltages "punch through" gate oxide  Irreversible damage to transistors  Solution: "Lightning Arrestor"(See Fig. 7-22, p. 389)  series resistor  clamping circuits

15. ECE 425 Spring 2007Lecture 20 - Chip-Level Design15 Input Pads  Basic Circuit:  Refinements:  NPN-transistors as clamps (see book)  MOS transistors as clamps (output drivers in bidirectional pad?)

16. ECE 425 Spring 2007Lecture 20 - Chip-Level Design16 Output Pads  large transistors used to drive external loads  note need for buffering to drive pad transistors

17. ECE 425 Spring 2007Lecture 20 - Chip-Level Design17 Bidirectional pads  Combine input, output circuit structures  Input mode: both output transistors OFF ("tristate" mode)  Output mode: one output transistor ON

18. ECE 425 Spring 2007Lecture 20 - Chip-Level Design18 The MOSIS 1.6µm pad frame  Developed by Jeff Sondeen, USC ISI  A set of pads designed to form a ring:  Bidirectional Pads  Input Pads (Bidirectional Pad with EN=0)  Output Pads (Bidirectional PAD with no output)  Power Supply Pads  "Empty" Pads  Connect by abutment to form complete ring  Pad Frame - fully assembled pad ring  More info available at: ftp://ftp.isi.edu/pub/sondeen/

19. ECE 425 Spring 2007Lecture 20 - Chip-Level Design19 MOSIS Pad | +-----+ +-+ | Frame SCNA.80.2000

20. ECE 425 Spring 2007Lecture 20 - Chip-Level Design20 MOSIS Pad Frame - IO Pad Cell 97 X 134 INInb InUnb ENout Vdd! Gnd!

21. ECE 425 Spring 2007Lecture 20 - Chip-Level Design21 IO Pad Design  Jeff Sondeen’s “ASCII Art” Schematic: +-----+ +----| PAD | | +-----+ +-+ | Vdd | \ +---------+ +-+ / 150 ohm | | |GND \ |+--+ +--+| ENABLE | +--0|| ||0--------- Vdd | | |+--+ +--+| | | | | | |+--+ | | +---------+-------------------0|| P | | | | |+--+ | ENABLE | |+--+ +--+| ENABLEbar | | ---------|---|| ||0--+------ +------+ | |+--+ +--+| | | | IN_unbuffered | | | | |+--+ | | +---------+-------|------------|| N +---+ | | | | |+--+ | | OUT | |+--+ +--+| | | \ / ------+---|| ||---+ GND 0 |+--+ +--+| | INbar | | +---+ +---------+ | | GND \ / 0 | IN Source:ftp://ftp.mosis.org/pub/sondeen/magic/SCNA.80.PADS.2000/README

22. ECE 425 Spring 2007Lecture 20 - Chip-Level Design22 Notes about ESD Protection* 1. Thick-Field Oxide transistor of size W/L= 600/3 microns, 2. 150 ohms N_diffusion resistor/diode, and 3. Tri-state output drivers as pair of diode clamps. “ESD results have been reported to exceed 2000 volts (in Orbit 2.0 um fab) but these results have not been confirmed by Mosis.” Source:ftp://ftp.mosis.org/pub/sondeen/magic/SCNA.80.PADS.2000/README

23. ECE 425 Spring 2007Lecture 20 - Chip-Level Design23 MOSIS Pad Frame - Vdd Pad Cell 97 X 134 Vdd! Gnd!

24. ECE 425 Spring 2007Lecture 20 - Chip-Level Design24 MOSIS Pad Frame - Analog, Power Pads analog (for V I, V E ) power (for V Rplus, V Rminus )

25. ECE 425 Spring 2007Lecture 20 - Chip-Level Design25 MOSIS Pad Frame - Corner Detail Vdd! Gnd!

26. ECE 425 Spring 2007Lecture 20 - Chip-Level Design26 A/D Project Pad Frame Location: /home/nestorj/PadFrame/adcframe04.mag 2570 1060 2570

27. ECE 425 Spring 2007Lecture 20 - Chip-Level Design27 ADC Frame Notes  Two projects per chip die  Chip “split” vertically  Design your layout top level cell to “drop into” padframe on left (or right) side

28. ECE 425 Spring 2007Lecture 20 - Chip-Level Design28 Coming Up  Floorplannning  Subsystem Design