1. Marc Riedel Ph.D. Defense, Electrical Engineering, Caltech November 17, 2003 Combinational Circuits with Feedback

2. Combinational Circuits Logic GateBuilding Block:

3. Combinational Circuits Logic GateBuilding Block: feed-forward device

4. Combinational Circuits “AND” gate 0 0 0 1 Common Gate: 0 0 1 1 0 1 0 1

5. Combinational Circuits “OR” gate 0 0 1 1 0 1 0 1 0 1 1 1 Common Gate:

6. Combinational Circuits “XOR” gate 0 0 1 1 0 1 0 1 0 1 1 0 Common Gate:

7. inputsoutputs The current outputs depend only on the current inputs. Combinational Circuits combinational logic

8. Combinational Circuits inputsoutputs The current outputs depend only on the current inputs. combinational logic gate

9. Generally feed-forward (i.e., acyclic) structures. Combinational Circuits x y x y z z c s

10. Generally feed-forward (i.e., acyclic) structures. Combinational Circuits 0 1 0 1 1 1 0 1 1 0 1

11. Feedback How can we determine the output without knowing the current state?... feedback

12. Feedback How can we determine the output without knowing the current state?... ? ? ?

13. Example: outputs can be determined in spite of feedback. Feedback

14. 0 0 Example: outputs can be determined in spite of feedback. Feedback

15. 0 0 0 0 Example: outputs can be determined in spite of feedback. Feedback

16. Example: outputs can be determined in spite of feedback. Feedback

17. 1 1 Example: outputs can be determined in spite of feedback. Feedback

18. 1 1 1 1 There is feedback is a topological sense, but not in an electrical sense. Example: outputs can be determined in spite of feedback. Feedback

19. Admittedly, this circuit is useless... Example: outputs can be determined in spite of feedback. Feedback

20. Rivest’s Circuit Example due to Rivest:

21. 0 0 Rivest’s Circuit

22. 0 0 0 Example due to Rivest:

23. Rivest’s Circuit Example due to Rivest: 0 0 0

24. 1 1 Rivest’s Circuit

25. 1 1 1 Example due to Rivest: Rivest’s Circuit

26. Example due to Rivest: 1 1 Rivest’s Circuit 1

27. Example due to Rivest: 3 inputs, 6 fan-in two gates. 6 distinct functions, each dependent on all 3 variables. Addition: OR Multiplication: AND

28. Rivest’s Circuit Individually, each function requires 2 fan-in two gates:

29. An equivalent feed-forward circuit requires 7 fan-in two gates.

30. A feedback circuit with fewer gates than any equivalent feed-forward circuit. Rivest’s Circuit 3 inputs, 6 fan-in two gates. 6 distinct functions.

31. Rivest’s Circuit n inputs 2n fan-in two gates, 2n distinct functions.

32. ... a Rivest’s Circuit gates An equivalent feed-forward circuit requires fan-in two gates.

33. Rivest’s Circuit n inputs 2n fan-in two gates, 2n distinct functions. A feedback circuit with the number of gates of any equivalent feed-forward circuit. 3 2

34. Prior Work Kautz first discussed the concept of feedback in logic circuits (1970). Huffman discussed feedback in threshold networks (1971). Rivest presented the first, and only viable, example of a combinational circuit with feedback (1977).

35. Prior Work F(X)F(X)G(X)G(X) e.g., add e.g., shift Stok discussed feedback at the level of functional units (1992). Malik (1994) and Shiple et al. (1996) proposed techniques for analysis. X G(F(X)) Y F(G(Y))

36. Questions 1.Is feedback more than a theoretical curiosity, even a general principle? 3 2 2.Can we improve upon the bound of ? 3.Can we optimize real circuits with feedback?

37. Key Contributions 2.Efficient symbolic algorithm for analysis (both functional and timing). 1.A family of feedback circuits that are asymptotically the size of equivalent feed-forward circuits. 2 1 3.A general methodology for synthesis.

38. Ph.D. Defense Present examples with same property as Rivest’s circuits. Illustrate techniques for analysis. Focus on synthesis: methodology, examples, optimization results.

39. Example not symmetrical 4 inputs 8 gates 8 distinct functions

40. Examples, multiple cycles, 3 inputs9 gates, 9 distinct functions

41. Example, 5 inputs 20 gates, 20 distinct functions. (“stacked” Rivest circuits)

42. ½ Example Generalization: family of feedback circuits ½ the size of equivalent feed-forward circuits. (sketch)

43. Analysis Functional analysis: determine if the circuit is combinational and if so, what values appear. Timing analysis: determine when the values appear. Contributions: 1.Symbolic algorithm based on Binary Decision Diagrams. 2.Optimizations based on topology (“first-cut” method).

44. Analysis 000000 0101 Assume gates each have unit delay. 0202 0101 0101 0202 0202 arrival times Explicit analysis:

45. 000000 0101 0202 0101 0101 0202 0202 010100 01011 0101 0303 0202 0404 Analysis Explicit analysis:

46. 010100 01011 0101 0303 0202 0404 n inputs  combinations Exhaustive evaluation intractable. Analysis Explicit analysis:

47. Symbolic analysis: 0101 : 1212 : 0303 : 1414 : Analysis similarly for

48. Symbolic analysis: 0101 0202 1 1212 Analysis undefined evaluates to 1 evaluates to 0

49. Symbolic analysis: 0 1-7 0 8-28 1 1-10 1 11-21 Analysis undefined evaluates to 1 evaluates to 0 range of values

50. Synthesis General methodology: optimize by introducing feedback in the substitution/minimization phase. Optimizations are significant and applicable to a wide range of circuits. Design a circuit to meet a specification.

51. Example: 7 Segment Display Inputs a b c d e f g Output 1001 0001 1110 0110 1010 0010 1100 0100 1000 0000 0123 xxxx 9 8 7 6 5 4 3 2 1 0

52. Example: 7 Segment Display a b c d e f g Output

53. Substitution/Minimization Basic minimization/restructuring operation: express a function in terms of other functions. Substitute b into a: (cost 9) a  ))(( 302321320 xxxxxxxxx  (cost 8) Substitute c into a: (cost 5) Substitute c, d into a: (cost 4) a  )( 323212 bxxxxxbx  a  cxxcx 321  a  dccx  1

54. Substitution/Minimization Berkeley SIS Tool a  ))(( 302321320 xxxxxxxxx  },,,{fdcb target function substitutional set a  dccx  1 low-cost expression   

55. Acyclic Substitution g f e b a c d Select an acyclic topological ordering: g f e d c b a       

56. g f d c b a       edcaxx  21 dccx  1 xxxxxxxxx  102213321 ))((dxxxxxx  102320 )(cdxx  10 )( Select an acyclic topological ordering: Cost (literal count): 37 Acyclic Substitution e   3 cxb d ba  f

57. Select an acyclic topological ordering: Nodes at the top benefit little from substitution. g f d c b a       edcaxx  21 dccx  1 xxxxxxxxx  102213321 ))((dxxxxxx  102320 )(cdxx  10 )( e   3 cxb d ba  f

58. Cyclic Substitution Try substituting every other function into each function: Not combinational! Cost (literal count): 30  0 1 ex dccx fba geex bcdx gxaxex egxxax      2 3 321 202 f g f d c b a       e 

59. Cost 30 Lower bound Cost 37 Upper bound Acyclic substitution Unordered substitution Cyclic solution? Cost 34

60. Cyclic Substitution g f e d c b a        Cost (literal count): 34 Combinational solution: xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f

61. Cyclic Substitution Cost (literal count): 34 Combinational solution: topological cycles g f e d c b a        xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f

62. Inputs x 3, x 2, x 1, x 0 Cost (literal count): 34 ba ga e e e c        1 no electrical cycles Cyclic Substitution g f e d c b a        xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f = [0,0,1,0]:

63. g f e d c b a        Cost (literal count): 34 ba ga e e e c        1        1 1 0 1 1 1 0 Cyclic Substitution no electrical cycles xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:

64. g f e d c b a        Cost (literal count): 34 ba ga e e e c        1        1 1 0 1 1 1 0 a b c d e f g Cyclic Substitution xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:

65. g f e d c b a        Cost (literal count): 34 ba ga e e e c        1        1 1 0 1 1 1 0 a b c d e f g Cyclic Substitution xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:

66. g f e d c b a        Cost (literal count): 34 ba ga e e e c        1        1 1 0 1 1 1 0 a b c d e f g Cyclic Substitution xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:

67. g f e d c b a        Cost (literal count): 34 Cyclic Substitution xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]:

68. g f e d c b a        Cost (literal count): 34 Cyclic Substitution ba a a 1 0 c        f xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]: no electrical cycles

69. g f e d c b a        Cost (literal count): 34        1 0 1 0 1 1 1 Cyclic Substitution ba a a 1 0 c        f xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f no electrical cycles Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]:

70. g f e d c b a        Cost (literal count): 34 a b c d e f g Cyclic Substitution        1 0 1 0 1 1 1 ba a a 1 0 c        f xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]:

71. g f e d c b a        Cost (literal count): 34 Cyclic Substitution        1 0 1 0 1 1 1 ba a a 1 0 c        f a b d e f g xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]: c

72. Synthesis Strategy: Allow cycles in the substitution phase of logic synthesis. Find lowest-cost combinational solution. 21213 321321 312321 )( )( )( xxxxxc xxxxxxb xxxxxxa       Collapsed: Cost: 17 321 1321 323 xxaxc cxxxxb xxbxa       Solution: Cost: 13

73. “Break-Down” approach Exclude edges Search performed outside space of combinational solutions cost 12 cost 13 cost 12 cost 13 combinational cost 14 Branch and Bound

74. “Build-Up” approach Include edges Search performed inside space of combinational solutions cost 17 cost 16 cost 15 not combinational cost 14 Branch and Bound cost 13 best solution

75. Implementation: CYCLIFY Program Incorporated synthesis methodology in a general logic synthesis environment (Berkeley SIS package). Trials on wide range of circuits –randomly generated –benchmarks –industrial designs. Consistently successful at finding superior cyclic solutions.

76. Benchmark Circuits Cost (literals in factored form) of Berkeley SIS Simplify vs. Cyclify Circuit# Inputs# OutputsBerkeleySimplifyCaltechCyclifyImprovement dc147393412.80% ex6811857610.60% p825141049013.50% t41281098918.30% bbsse11 11810610.20% sse11 11810610.20% 5xp171012310911.40% s38611 13111313.70% dk17101116013615.00% apla101218513129.20% tms81618515814.60% cse11 21217716.50% clip9521318911.30% m281623120710.40% s510251326022712.70% t1212327320624.50% ex1132430927610.70% exp81832026218.10%

77. Benchmarks Example: EXP circuit Cyclic Solution (Caltech CYCLIFY ): cost 262 Acyclic Solution (Berkeley SIS ): cost 320 cost measured by the literal count in the substitute/minimize phase

78. Discussion A new definition for the term “combinational circuit”: a directed, possibly cyclic, collection of logic gates. Most circuits can be optimized with feedback. Optimizations are significant. Paradigm shift:

79. Current Work Implement more sophisticated search heuristics (e.g., simulated annealing). Extend ideas to a decomposition and technology mapping phases of synthesis. Address optimization of circuits for delay with feedback.

80. Future Directions inputsoutputs data structure  Structured Network Representations databases, biological systems,...

81. Binary Decision Diagrams Introduced by Lee (1959). Popularized by Bryant (1986). Graph-based Representation of Boolean Functions compact (functions of 50 variables) efficient (linear time manipluation) Widely used; has had a significant impact on the CAD industry. 0 1 1 0

82. Binary Decision Diagrams 0 1 1 0 1111 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 x 2 x 3 x f 0 1 BDDs generally defined as Directed Acyclic Graphs Graph-based Representation of Boolean Functions

83. Binary Decision Diagrams Short described a cyclic structure for a BDD variant (1960). We suggest cycles are a general phenomenon. 001011

84. Binary Decision Diagrams Short described a cyclic structure for a BDD variant (1960). We suggest cycles are a general phenomenon. 001011 0 ** 0 0 1011 1

85. Binary Decision Diagrams Short described a cyclic structure for a BDD variant (1960). We suggest cycles are a general phenomenon. 001011

86. Binary Decision Diagrams Short described a cyclic structure for a BDD variant (1960). We suggest cycles are a general phenomenon. 001011 Future research awaits...