1. SCOTT MILLER, AMBROSE CHU, MIHAI SIMA, MICHAEL MCGUIRE SMILLER@ECE.UVIC.CA ReCoEng Lab DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF VICTORIA VICTORIA, B.C., CANADA VLSI Implementation of a Cryptography-Oriented Reconfigurable Array DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

2. Outline Motivation and Problem Statement Overview of Current FPGAs Limitations for Cryptography Carry Lookahead Addition CryptoRA Tile Implementation, Split LUT Simulation Framework Results Conclusions DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

3. Motivation Problem Cryptography on mobile, embedded systems ASICs are expensive  Recurring engineering, quick obsolescence Poor long-integer arithmetic support in current FPGAs Design Constraints Low added complexity No (negligible) impact on reconfigurability “Cheap” solution DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

4. Overview of FPGAs Grid of computing units Mesh of configurable interconnection busses Emulate any digital logic function Global Interconnect slow CLB DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

5. Overview of FPGAs DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada Xilinx Virtex-II 4-input LUT Support for ripple- carry and carry- lookahead adders

6. Carry-Lookahead Addition Ripple Carry Adders have serial delay Carry Lookahead calculate carries in parallel Can use hierarchies of CLA adders to speed-up long-operand calculations OPERANDS FOR CLA 1 + 1 = Generate 1 + 0 = Propagate 0 + 1 = Propagate 0 + 0 = Nothing

7. FPGAs: Limitations for Cryptography Poor support for long-integer arithmetic  Long ripple-carry chains (with global interconnects) ‏  Fast-adders still require multiple stages of global-interconnects Same difficulties for comparison operations  Required in most common ECC and RSA algorithms DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

8. FPGAs: Limitations for Cryptography DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

9. Proposed Solution: CryptoRA Based on Xilinx architecture Additional fast-path provided for simultaneous Carry, Propagate signals Extends fast-path across in rows as well as columns Splits LUT to handle subtraction, etc. DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

10. CryptoRA: Split LUT DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

11. VLSI Modeling DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

12. Simulation Framework All designs simulated in 65nm technology  Simulated with Cadence Spectre simulator  Average taken of 10 Monte Carlo runs with process variation and mismatched included Simulated simplified CLB models  Many components outside the scope of this research  Respective loads for omitted modules were included Timing simulated at every point of interest in the LUT -> Fast chain path to find all timing trade-offs DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

13. Results: Split LUT DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

14. Results: Split LUT DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

15. Results - Discussion Performance boost of added carry-chain and additional fast-path cannot be directly quantified  Dependence on physical FPGA itself, and operand word-length Hierarchical carry-lookahead adders show promise with the new chains for increased performance Example calculations are given in the paper Performance comes at 2.5% area increase over smallest reference structure DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

16. Conclusions Split LUT structure enhances performance at minor (2.5%) area penalty Increased speed in carry chain and avoiding global interconnect improves long-integer operation performance Line-loading overhead from extra fast-chains is very small This device shows promise for performing cryptographic operations. DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada

17. Thank You for Listening Any Questions? Scott Miller smiller@ece.uvic.ca http://www.ece.uvic.ca/~smiller DSD 2008 - Parma, Italy ReCoEng Lab, University of Victoria, Canada