1. Uli Schäfer 1 JEM1: Status and plans Hardware status Firmware status Plans

2. Uli Schäfer 2 JEM1 16 x 6-channel de- serialisers : SCAN921260 on 4 Input daughter modules w. XC2V1500. 3.3V G-link / Opto transceiver daughter module Jet and Sum Processors XC2V2000 (BF package). Configuration : SystemACE 88 pair VMEVME each 165 pins FIO 60 bit @ 80Mb/s TTCdec CAN System ACE 3 x 40 bit @ 40 Mb/s DES Input 2 B 1 A 0 V 60 40 Input 5 E 4 D 3 C Input 8 H 7 G 6 F Input -- 10 X 9 W DAQ/Timing/VME To JMM G 16 Jet R S T U Sum DAQ To SMM ROI Opto clock mirror Opto

3. Uli Schäfer 3 JEM1 H/W & F/W Status Input daughters: 18 working modules available 2 required rework Main board: 4 modules available 3 Fully working. Few bug fixes required (few tracks missing, 2LEDs missing few pull-ups, some CAN mods, ACE config hand-tuned). 4th module: configuration and B/scan problems G-link daughters: 20-bit version successfully tested (electrical and optical) 3.3V 16-bit G-link dual opto transmitter module tested Current version is 16-bit, opto transceivers: 2 pcs available, seem to work, will be tested at RAL next week. Firmware : stable

4. Uli Schäfer 4 Module-4 problems With minor tuning of TCK edges (RC or slow driver) 3 modules could be made work with system ACE configurator. However: Module #4 B/SCAN does not work: Full chain not always visible (sum, jet, 4xinput processor). Dead FPGAs have TDO=‘1’ =const. Behaviour unpredictable. All external controls and supplies look ok. No excessive noise visible. JTAG problems obstruct test of suspected connectivity problem on one VME line SystemACE configuration impossible Xilinx looking into it, some suggestions were made, no success yet. Since the problem might be related to the need for tuning the TCK on the working modules, we do not dare going into production now!

5. Uli Schäfer 5 Plans Need to fix the JTAG problem first If the underlying cause cannot be found we need to design for redundancy: Add a configurator daughter module, ie. 6 rather than 5 daughter modules per JEM now Feed all JTAG lines of all FPGAs to the configurator in star topology Feed all serial configuration lines of all FPGAs to the configurator Provide slave serial and JTAG configuration circuitry on the configurator Be prepared to iterate the configuration module  Try and have FDR in January either based on current design if the problems can be understood. Otherwise decide in favour of configurator module.