1. Group 2 Week 7 Presentation AlexDaveKevinMike

2. Jumps/Branches Implemented the last of the Jumps/Branches into our design. Implemented the last of the Jumps/Branches into our design. Placed the adder into the ID stage rather than use our ALU in the EX stage. Placed the adder into the ID stage rather than use our ALU in the EX stage.

3. Final Design Debugged our entire pipeline processor. Debugged our entire pipeline processor. We have no schematic or sheet errors and the design is able to compile. We have no schematic or sheet errors and the design is able to compile.

4. LHI Implemented LHI into the final design. Implemented LHI into the final design. Used our immediate concatenator Used our immediate concatenator

5. Special Register Implemented it into the final design. Implemented it into the final design. Had to add more control signals. Had to add more control signals. We are now able to finish RFE and TRAP. We are now able to finish RFE and TRAP.

6. ASM Files Began translating the ASM files into files that will be recognized by Quiksim. Began translating the ASM files into files that will be recognized by Quiksim. First we downloaded the test file and placed 0x1000 into registers R1 and R29. First we downloaded the test file and placed 0x1000 into registers R1 and R29. Next we used dlxasm to convert the file from.s to.l. Next we used dlxasm to convert the file from.s to.l. We then used full-translate.pl to get a.dat. We then used full-translate.pl to get a.dat. Finally we used smartmem.pl to break the file into 4 separate files, one for each byte. Finally we used smartmem.pl to break the file into 4 separate files, one for each byte.

7. ASM FILES Have quicksort ready to be tested once our final specs are ready. Have quicksort ready to be tested once our final specs are ready.