1. Improving IPC by Kernel Design Jochen Liedtke Presented by Ahmed Badran

2. Contents Why optimize IPC? Previous IPC optimizations Optimizations Architectural Algorithmic Interface Coding Performance

3. Why optimize IPC Microkernels rely heavily on IPC Moving services out of the kernel and running them in user space Many OSes rely on IPC as the sole communication mechanism, e.g. Mach The intention is to have domain (address space) protection as well as high performance!

4. Previous IPC Optimizations Using registers to pass short messages SRC RPC: Special path through scheduler for RPC context switching and message buffers shared across all domains (reduced security) LRPC optimizes the “common” case as we’ve seen before

5. Architectural Optimizations Reduced number of system calls (2 instead of 4) Package several messages in one “send” potential savings Memory Object references (optional) Copied Lazily Passed as address & length pairs Indirect string (optional) Copied strictly Direct String (mandatory) Copied strictly

6. Architectural Optimizations (2) Direct Transfer by Temporary Mapping One kernel stack per thread TCBs as an array mapped to all address spaces

7. Algorithmic Optimizations Thread Identifier (simple, inexpensive manipulation logic) Implementing queues as doubly-linked lists that are chained in the TCBs Timeout and wakeup queues Lazy Scheduling to alleviate the need for insertion and deletion from ready and wakeup queues

8. Algorithmic Optimizations (2) Direct Process Switching (handoff & fairness) Short messages via registers

9. Interface Optimizations Avoiding unnecessary copies (packing messages into a single “send”, using same data structure for input & output buffer) Parameter passing (via registers as much as possible, avoid saving & restoring unneeded registers)

10. Coding Optimizations Reducing cache misses (pay attention to data & code placement) Minimizing TLB misses Part of tcb 1 rest of tcb 1 Part of tcb 2 rest of tcb 2 VS. rest of tcb 1Part of tcb 1 rest of tcb 2Part of tcb 2 Cache

11. Coding Optimizations (2) Segment registers General purpose registers Process switch

12. Results