1. Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #10: Smart Cart 525 Stage X: 28 Mar. 2005 Chip Level Layout 2

2. Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design Component Layout Functional Block Layout DRC of functional blocks LVS of functional blocks Chip Level Layout Full chip LVS!!!!  Simulations (50%) Schematic with loaded inputs/outputs Extracted, ExtractedRC view

3. Design Decisions Changed register type after having problems with Analog Simulation Adding more buffers to design

4. Previously (320.220 x 293.355)

5. Currently (323.955 x 296.1)

6. Design Specifications Area:95,923 μm 2 # of Transistors:21,944 Density: (transistors/μm 2 ).23 Aspect ratio:1.09

7. LVS Verification Net-list summary for /afs/ece.cmu.edu/usr/bgai/cds/LVS/layout/netlist count 6965nets 87terminals 7752pmos 14192nmos Net-list summary for /afs/ece.cmu.edu/usr/bgai/cds/LVS/schematic/netlist count 7066nets 87terminals 101cds_thru 7752pmos 14192nmos Terminal correspondence points 1Clk 2Clk2 3done 4gnd! 5input16bit 6input16bit 7input16bit 8input16bit 9input16bit 10input16bit 11input16bit 12input16bit 13input16bit 14input16bit 15input16bit 16input16bit 17input16bit 18input16bit 19input16bit 20input16bit 21lastPrice 22lastPrice 23lastPrice 24lastPrice 25lastPrice 26lastPrice 27lastPrice 28lastPrice 29lastPrice 30lastPrice 31operationCode 32operationCode 33operationCode 34out 35out 36out 37out 38out 39out 40out 41out 42out 43out 44out 45out 46out 47out 48out 49out 50out 51out 52out

8. 53out 54out 55text_out 56text_out 57text_out 58text_out 59text_out 60text_out 61text_out 62text_out 63text_out 64text_out 65text_out 66text_out 67text_out 68text_out 69text_out 70text_out 71text_out 72text_out 73text_out 74text_out 75text_out 76text_out 77text_out 78text_out 79text_out 80text_out 81text_out 82text_out 83text_out 84text_out 85text_out 86text_out 87vdd! The net-lists match. layout schematic instances un-matched00 rewired00 size errors00 pruned00 active2194422045 total2194422045 nets un-matched00 merged00 pruned00 active69657066 total69657066 terminals un-matched00 matched but different type00 total8787

9. Simulations: Top (Total Output--Schematic)

10. Simulations: Top (Last Price Output--Schematic)

11. Simulations: Encryption (Final Output--Schematic)

12. Simulations: Encryption (ROM) Extracted Rise Time: 941.308 ps Fall Time: 698.145 ps

13. Simulations: Arithmetic Blocks Multiplier  Schematic Rise Time: 144.599 ps Fall Time: 94.4327 ps Propagation Time: 425 ps  ExtractedRC Rise Time: 163.18 ps Fall Time: 93.65 ps Propagation Time: 3.53 ns Adder  Schematic Rise Time: 144.708 ps Fall Time: 96.0891 ps Propagation Time: 512.017 ps  ExtractedRC coming soon

14. Simulations: SRAM Schematic Rise Time: 192.883 ps Fall Time: 103.013 ps Prop. Time: 1.112 ns ExtractedRC Rise Time: 275.000 ps Fall Time: 147.000 ps Prop. Time: 947.000 ps

15. Problems & Questions White space reduction  Buffers expected to fill some of this space Adder is weird  Having to go through so many transmission gates may be a problem