1. Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 4 MAD MAC 525 15 th February, 2006 Gate Level Design W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

2. MAD MAC 525 Status: Project chosen Specifications defined Architecture Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan (revised & Updated) Schematic (adder)  To be done  Layout  Extraction, LVS, post-layout simulation

3. Multiply Add (MAD) / Multiply Accumulate Unit (MAC) Executes function AB+C on 16 bit floating point inputs Multiply and add in parallel to greatly speed up operation Rounding is only performed only once so greater accuracy than individual multiply and add functions. MAD MAC accelerates FP16 blending to enable true HDR graphics Bright things can be really bright Dark things can be really dark And the details can be seen in both Recap - MAD MAC 525

4. Design Decisions Using n pass shifters instead of regular gates for the muxes –Increases speed --- –Reduces transistor count –Reduces area –Complexity of the project remains the same

7. Block Diagram RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Reg Y Leading 0 Anticipator 10 5 5 5 14 35 22 5 4 36 14 10 1 5 5 Input Output 16

8. Updated Estimated Transistor Count n-pass gates Registers (I/O, pipelining,threading) 18001800 Carry-Save Multiplier 35003500 Carry-Select Adder/Subtractor 37003700 Alignment Shifter 5301500 Leading 0 Anticipator 350 350 Normalize 9003400 Rounding 300 300 Exponents 700 700 Total 11780 15250

9. Estimated area (in um sq) n-pass  Registers 9000  Multiplier 25000  Adder 26500  Align 3800  Leading zero counter 2500  Normalize 6500  Round 2000  Exponent calc 5000 Total 80300

10. Multiplier Align C Reg A Reg B Exp Calc Reg C Pipeline Reg Adder Ld Zero Pipeline Reg Normalize Round Reg Y Main Floorplan

11. Multiplier

12. And Array 726 transistors Full Adder Array 2640 transistors Input From Reg A 10 Input from Reg B Input To Adder 22

13. Schematics Multiplier: 11 x 11 Carry-Save Multiplier

14. Schematics Leading Zero Counter: Carry-Save Adder to count the leading zeroes of C

15. Schematics Align Exponents: N-pass shifter

16. Schematics I bit N-pass shifter used in the align block

17. Schematics Normalize: n-Pass Shifter to shift the result of the adder by the amount given by the Leading Zero Counter

18. Shifter for the Normalize

19. Schematics Round: Incrementer and Shifter

20. Pipeline Reg Critical Path RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Reg Y Leading 0 Anticipator 10 5 5 5 1435 22 5 4 36 14 10 1 5 5 Input 16

21. Questions?