1. ECE 667 - Synthesis & Verification - Lecture 18 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Word-level (decision) Diagrams BMDs, TEDs

2. ECE 667 - Synthesis & Verification - Lecture 18 2 Outline Review of design representations – –common representations of Boolean and arithmetic functions Motivation for word-level diagrams – –RTL synthesis, verification and verification – –Need more abstract representation Higher level “decision” diagrams – –Binary Moment Diagram (BMD) – word level – –Taylor Expansion Diagram (TED) – symbolic level

3. ECE 667 - Synthesis & Verification - Lecture 18 3 Motivation – Design Representation Complex RTL designs – –Data flow and control Interaction – –Arithmetic and Boolean – –Data flow and control B A s 1010 F D akak bkbk > + * - Validate an RTL design –Generate functional tests (SAT problem) Verify equivalence of two RTL designs B A s 0101 F D akak bkbk <= + * -

4. ECE 667 - Synthesis & Verification - Lecture 18 4 Design Representations Boolean functions ( f : B  B ) – –Truth table, Karnaugh map – –SoP, PoS, ESoP – –Reed-Muller expansions (XOR-based) – –Decision diagrams (BDD, ZDD, etc.) Arithmetic functions ( f : B  Int ) – –Binary Moment Diagrams (*BMD, K*BMD, *PHDD) – –Multi-terminal, Algebraic Decision Diagrams (ADD) Arithmetic functions (f : Int  Int ) – –Taylor Expansion Diagrams (TED)

5. ECE 667 - Synthesis & Verification - Lecture 18 5 Canonical Representations Each minimal, canonical representation is characterized by – –Decomposition type Shannon, Davio, moment decomposition, Taylor exp., etc. – –Reduction rules Redundant nodes, isomorphic sub-graphs, etc. – –Composition method (“APPLY”, or compose rule) What they represent – –Boolean functions (f : B  B) – –Arithmetic functions (f : B  Int ) – –Algebraic expressions (f : Int  Int )

6. ECE 667 - Synthesis & Verification - Lecture 18 6 Decomposition Types Shannon expansion (used in BDDs) f = x f x + x’ f x’ Moment decomposition (BMD): replace x’=1-x, f = x f x + (1-x) f x’ = f x’ + x f  x where f  x = f x - f x’ – –also called positive Davio decomposition

7. ECE 667 - Synthesis & Verification - Lecture 18 7 Binary Moment Diagrams (* BMD ) Devised for word-level operations, arithmetic Based on modified Shannon expansion (positive Davio) f = x f x + x’ f x’ = x f x + (1-x) f x’ = f x’ + x (f x - f x’ ) = f x’ + x f  x where f x’ = f x=0, is zero moment f  x = (f x - f x’ ) is first moment, first derivative Additive and multiplicative weights on edges (*BMD)

8. ECE 667 - Synthesis & Verification - Lecture 18 8 *BMD - Construction Unsigned integer: X = 8x 3 + 4x 2 + 2x 1 + x 0 X(x 3 =1) = 8 + 4x 2 + 2x 1 + x 0 x3 X(x 3 =0) = 4x 2 + 2x 1 + x 0 X  x3 = 8 8 x2 x1 x0 421 0 1 0 x1 x2 1 2 4 x3 8 BMD *BMD Multiplicative edges

9. ECE 667 - Synthesis & Verification - Lecture 18 9 *BMD - Word Level Representation Efficiently modeling symbolic word-level operators Word level 4 1 0 x0 x1 x2 1 2 4 y0 y1 y2 2 1 1 0 x0 x1 x2 y0 y1 y2 1 2 4 2 4 1 Word level X+Y X Y

10. ECE 667 - Synthesis & Verification - Lecture 18 10 Limitations of * BMD *BMD requires bit-level expansion – –works on Boolean fundamentals – –modeled with constant and first moment only BMD representation of F = X 2, X={x 2, x 1, x 0 } 1 0 x0 x1 x2 x1 x0 2 4 8

11. ECE 667 - Synthesis & Verification - Lecture 18 11 Are BDDs and *BMDs sufficiently High Level? Both are canonical for fixed variable order BDDs – –Good for equivalence checking and SAT – –Inefficient for large arithmetic circuits (multipliers) BMDs – –Efficient for word-level operators – –Less compact for Boolean logic than BDDs – –Good for equivalence checking, but not for SAT – –Insufficient for high-order arithmetic expressions

12. ECE 667 - Synthesis & Verification - Lecture 18 12 Symbolic Level Representation Can we devise a more general representation than “word-level” *BMD ? X + Y 1 0 X Y Symbolic level X Y 1 0 X Y Symbolic level

13. ECE 667 - Synthesis & Verification - Lecture 18 13 Taylor Expansion Diagram (TED) Function F treated as a continuous functionFunction F treated as a continuous function Taylor Expansion (around x=0):Taylor Expansion (around x=0): F(x) = F(0) + x F’(0) + ½ x 2 F’’(0) + … Notation:Notation: –F 0 (x) = F(x=0) 0-child - - - - - - –F 1 (x) = F’(x=0) 1-child ---------- –F 2 (x) = ½ F’’(x=0) 2-child ====== –etc. F(x) = F 0 (x) + x F 1 (x) + x 2 F 2 (x) + … F(x) = F 0 (x) + x F 1 (x) + x 2 F 2 (x) + … x F 0 (x) F 1 (x) F 2 (x) … F(x)

14. ECE 667 - Synthesis & Verification - Lecture 18 14 Construction - Your First TED F = A 2 B + 2C + 3 A F 0 (A) = F | A=0 = 2C + 3 F 1 (A) = F’ | A=0 = 2AB | A=0 = 0 F 2 (A) = ½ F’’ | A=0 = B B 10 A G= 2C + 3 H 0 (B) = B | B=0 = 0 H 1 (B) = B’ = 1 C G 0 (C) = (2C+3) | C=0 = 3 G 1 (C) = (2C+3)’ = 2 B C 23 H (normalization will move weights from terminals to edges)

15. ECE 667 - Synthesis & Verification - Lecture 18 15 TED – a few Examples 1 x0 x1 x2 x3 2 4 1 0 1 x0 x1 x2 1 1 1 4 4 8 16 64 1 1 (A+B)C +1 1 0 B C A 1 (A+B)(A+2C) 1 0 B C A B 1 2

16. ECE 667 - Synthesis & Verification - Lecture 18 16 TED Reduction Rules - 1 a) Nodes with all empty edges 1.Eliminate redundant nodes: b) with only a constant term 0 f = 0 a 2 + 0 a + g(b) = g(b), independent of a f = 0 a 2 + 0 a + 0 = 0 a 0 f a b 0 f g b g

17. ECE 667 - Synthesis & Verification - Lecture 18 17 TED Reduction Rules - 2 2. Merge isomorphic subgraphs (identical nodes) (A 2 + 5A + 6)(B + C) A B C 10 01 1 B B C C 6 5 1 A B C 01 6 51

18. ECE 667 - Synthesis & Verification - Lecture 18 18 TED Normalization TED is normalized if – –there are no more than two terminal nodes: 0 and 1 – –weights of edges of a given node must be relatively prime (to allow sharing isomorphic graphs) 2 6 B A 2 2A + 2B + 6 normalized 3 0 B A 1 2 2 1 3 B A 1 2 1 1 2(A + B + 3)

19. ECE 667 - Synthesis & Verification - Lecture 18 19 Normalization - Example (A 2 + 5A + 6)(B + C) A B C 50 01 6 B B C C A B C 01 6 51 A B C 10 01 1 B B C C 6 5 1

20. ECE 667 - Synthesis & Verification - Lecture 18 20 TED: Composition (APPLY operation) Operation depends on relative order of variables x, y – –if x = y, then z = x, and h(x) = f(x) OP g(x) = f 0 (x) OP g 0 (y) + x [f 1 (x) OP g 1 (y)] + x 2 [f 2 (x) OP g 2 ], … – –if x > y, then z = x, and h(x) = f 0 (x) OP g(y) + x [f 1 (x) OP g(y)] + x 2 [f 2 (x) OP g], … – –else …. u f x v g y OP = Recursive composition of nodes, starting at the top h = f OP g q z OP = (+, -, )

21. ECE 667 - Synthesis & Verification - Lecture 18 21 APPLY Operation - Example * A+B 01 4 3 A B = 3 5 4 6 A 0 5 C A+2C 01 6 5 A 2 1 5 B 0 0 2 1 0 1 2 C C 1 5 1 0 1 2 + 1 B 3 1 0 1 1 C 0 7 2 B 0 8 1 + = 0+70+7 8+78+7 B 0+00+0 0+20+2 1 C (A+B)(A+2C) 2 0 1 C A BB 2

22. ECE 667 - Synthesis & Verification - Lecture 18 22 Properties of TED Canonical (if ordered, reduced, normalized) Linear for polynomials of arbitrary degree Can contain word-level, and Boolean variables TEDs can be manipulated (add, mult) using simple APPLY operator, similar to BDD or BMD: f = g + h; APPLY(+, g, h) f = g * h; APPLY(*, g, h) f = g – h; APPLY(+, g, APPLY(*, -1, h))

23. ECE 667 - Synthesis & Verification - Lecture 18 23 Properties of TED Canonical Compact Linear for polynomials of arbitrary degree – –TED for X k, k = const, with n bits, has k(n-1)+1 nodes. Can contain symbolic, word-level, and Boolean variables It is not a Decision Diagram 1 x0 x1 x2 x3 2 4 1 0 1 x0 x1 x2 1 1 1 4 4 8 16 64 1 1 X 2 =(8x 3 +4x 2 +2x 1 +x 0 ) 2 n = 4, k = 2

24. ECE 667 - Synthesis & Verification - Lecture 18 24 TED for Boolean logic AND 1 0 x y x  y = x y 10 x 1 x’ = (1-x) NOT OR x  y = (x + y – x y) 1 0 x yy 1 XOR x 1 0 yy -2 1 x  y = (x + y – 2 x y) Needed to model arithmetic-Boolean interface Same as *BMD for Boolean logic

25. ECE 667 - Synthesis & Verification - Lecture 18 25 TED for Arithmetic Circuits Arithmetic circuits contain related word-level (A, B) and Boolean (a k, b k ) variables A = [ a n-1, …, a k, …,a 0 ] = 2 (k+1) A hi + 2 k a k + A lo B A s1s1 1010 F1F1 D akak bkbk > + * - s 1 = a k (1-b k ) A hi A lo 0 1 2k2k 2 (k+1) AhiAhi akak A lo

26. ECE 667 - Synthesis & Verification - Lecture 18 26 Applications to RTL Verification Equivalence checking with TEDs – –interacting word-level and Boolean variables A B s2s2 0101 F2F2 bkbk akak * * - D B A s1s1 1010 F1F1 D akak bkbk > + * - F 1 = s 1 (A+B)(A-B) + (1-s 1 )D s 1 = (a k > b k ) = a k (1-b k ) F 2 = (1-s 2 ) (A 2 -B 2 ) + s 2 D s 2 = a k ’  b k = 1 - a k + a k b k A = [a n-1, …,a k,…,a 0 ] = [A hi,a k,A lo ], B = [b n-1, …,b k,…,b 0 ] = [B hi,b k,B lo ]

27. ECE 667 - Synthesis & Verification - Lecture 18 27 RTL Verification – cont’d. Related word-level and Boolean variables F 1 = s 1 (A+B)(A-B) + (1-s 1 )D A = [A hi, a k, A lo ] B = [B hi, b k, B lo ] s 1 = (a k > b k ) = a k (1-b k ) 1 akak 1 A hi D akak bkbk bkbk B hi A lo B lo 2k2k 1 2 2k+2 2 k+2 -2 k+2 -2 2k+2 F 1 = F 2 A lo 1 2 k+1 2k2k This is a common (isomorphic) TED for both designs: TED(F1)  TED(F2)

28. ECE 667 - Synthesis & Verification - Lecture 18 28 Verification of Algorithmic Specifications x x x x FAB1 FAB2 FAB3 A0 A1 A3 A2 B0 B1 B2 B3 FFT(A) FFT(B) IFFT0 IFFT1 IFFT3 IFFT2 InvFFT(FAB) A[0:3] B[0:3] C0 C1 C2 C3 Conv(A,B) Use TED to prove equivalence: IFFT i =C i  

29. ECE 667 - Synthesis & Verification - Lecture 18 29 Summary Features of TED – –Canonical, minimal, normalized – –Compact (linear for polynomials) – –Represents word-level blocks and Boolean logic Applications – –Equivalence checking, RTL verification – –Symbolic simulation (representation) – –Algorithm verification Open problems – –Satisfiability, functional test generation – –Finite precision arithmetic