1. Nov. 29, 2005 ELEC6970-001 Class Presentation 1 Reducing Voltage Supply Jins Davis Alexander

2. Nov. 29, 2005 ELEC6970-001 Class Presentation 2 Objective… To reduce the power consumption by reducing VDD supply voltage and seeing its effect on power, delay and area. No effect on area.

3. Nov. 29, 2005 ELEC6970-001 Class Presentation 3 What We Know…. Power Consumption is a quadratic function of Voltage. Decrease in supply Voltage increases the overall delay.

4. Nov. 29, 2005 ELEC6970-001 Class Presentation 4 Power and Delay Power = CV DD 2 Delay= KV DD ─────── (V DD – V t ) α (from alpha-power model)

5. Nov. 29, 2005 ELEC6970-001 Class Presentation 5 What I have done… Designed N*N array multiplier using VHDL. Used ELDO for power analysis and calculation of delay. First simulated basic cell and found delay of Sumout to be greater than Cout.

6. Nov. 29, 2005 ELEC6970-001 Class Presentation 6 Forced pulse signals for all possible vectors at inputs A and B for a 4x4 multiplier. Compared signal A[0] with Sum[2N-2] to calculate the overall worst case delay.

7. Nov. 29, 2005 ELEC6970-001 Class Presentation 7 Results of 4x4 array multiplier. VoltageAvg.Power (uW)Delay (ns) 1.8106.321.76 1.566.431.934 1.236.492.34 121.713.99

8. Nov. 29, 2005 ELEC6970-001 Class Presentation 8 % Results Voltage(% Decrease) Avg Power(% Decrease) Delay (% Increase) 16.7%37.5%10% 33.3%65.6%33% 44.4%79.5%127%

9. Nov. 29, 2005 ELEC6970-001 Class Presentation 9 Dynamic Power vs. Voltage

10. Nov. 29, 2005 ELEC6970-001 Class Presentation 10 Delay vs. Voltage

11. Nov. 29, 2005 ELEC6970-001 Class Presentation 11 Static Power vs. Voltage

12. Nov. 29, 2005 ELEC6970-001 Class Presentation 12 Conclusion. Reducing Voltage decrease power significantly. However at lower voltages the delay increase is very significant. Transistor sizing, parallel processing can help reduce the overall delay.

13. Nov. 29, 2005 ELEC6970-001 Class Presentation 13 THANK YOU.