1. 1 64-Bit AND Gate Phong Nguyen Steve Turner Harpreet Dhillon Mahrang Saeed Advisor: Dave Parent 5/8/06

2. 2 Agenda Abstract Introduction –What we learned –What it’s used for –Theory Project Summary Project Details Results Time schedule Conclusions

3. 3 Abstract Designed a 64 bit AND gate that operates at 400 MHz and occupies an area of 807x320um 2.

4. 4 Introduction By doing this project, we learned how to do a full custom IC design. 64-bit AND gate is useful in doing 64-bit processing. A/32B/32Y/1 000 010 100 111

5. 5 Project Summary 400 Mhz 64 bit and gate 3.65 % error between worst case and best case input vectors Tplh equals 2.1ns and Tphl equals 1.57ns Power = 2.35 mW @ 400 MHz Power = 1.17 mW @ 200 MHz

6. 6 Longest Path Calculations WnWpCintCloadCint+Cg 8bitcell nand23.00E-04 5.00E-151.51E-142.01E-14 nor23.00E-046.00E-045.00E-157.55E-151.26E-14 nand22.25E-04 5.00E-151.01E-141.51E-14 last8bitcell nor21.95E-044.05E-045.00E-151.08E-141.58E-14 nand23.15E-043.30E-045.00E-152.27E-142.77E-14 nor23.75E-049.75E-045.00E-153.00E-143.50E-14 dff NAND2 (Slave)8.10E-04 5.00E-151.01E-141.51E-14 Driver Mux (Slave)9.45E-045.40E-045.00E-152.69E-143.19E-14 NAND2 (Master)7.50E-048.40E-045.00E-152.49E-142.99E-14 Driver Mux (Master)7.80E-044.35E+005.00E-152.66E-143.16E-14

7. 7 Schematic with worst case path blackcell: flip-flop x 64 redcell: 8bit cell x 8 bluecell: last 8bit cell

8. 8 Final Layout

9. 9 Verification

10. 10 NCVerilog only time when all bits are 1, output is 1

11. 11 Transient Simulation tphl

12. 12 Transient Simulation tplh

13. 13 Time Schedule Verifying Timing Layout Post Extracted Timing Verifying Logic Time 2 Weeks 1 Week 2 Weeks 1 Week

14. 14 Lessons Learned Before starting layout spend time on making a floor plan Using Cell based design makes it easy & It reduces debug time Time management is the main key to complete any project Also pay attention to best case delay as well See professor more often, keep updated

15. 15 Summary It can be used for 64 Bit Processing Max. Frequency - 400 Mhz Error between worst and best case input vectors is only 3.65 % Tplh equals 2.1ns and Tphl equals 1.57ns Power = 2.35 mW @ 400 MHz It can be used in a bigger project

16. 16 Acknowledgements Thanks to Cadence Design Systems for the VLSI lab Thanks to Professor Parent for his time & guidance