1. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Breakout Session: Controls Physics Requirements and Technology Choices for LCLS Instrumentation & Controls

2. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Accelerator Physics Driving Controls Design Precision beams Low emittance Short bunch Single pass Every shot different Simultaneous Single shot Read all devices PS control Process/respond in < 1/120 th sec. Feedback Trajectory Bunch length Energy Timing distribution RF Phase control Applications Machine tuning Compatibility Other programs Old controls

3. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Critical design choices for instrumentation Power supply control and regulation Stability and latency time for fast feedback control Beam position monitor signal processing Resolution, drift, calibration Timing distribution Precision, stability, synchronization, SLC compatibility RF stabilization Beam based feedback Single-shot CSR bunch length monitors

4. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Power supply system requirements Stability requirements 10 ppm in the chicane bends Response time Low control-system latency for feedback <1 ms Commercial components Reliability

5. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Digital PS controller developed by SLS PWM digital regulation loop controls AC converter power module PWM is a digital process already Avoids unnecessary digital => analog => digital conversion Only source of drift in an all digital system is ADC reference voltage High-speed links, minimal latency Fully developed at SLS with proven performance Fully integrated into EPICS controls Now adopted by several large accelerator projects, including Diamond Light Source

6. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Power supply controller system layout IOCIOC EPICS Power Supply DSP Controller ADC Card PWM AC Converter load DCCT 8 ch VME card AC line 5MHz Optical fiber PWM signal Monitor signals

7. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Courtesy F. Jenni, PSI

8. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 PSI Digital Power Supplies ADC/DAC Card DSP Controller DCCT 0..6 Slaves Magnet PWM Signal Fast Optical Link (5 MHz) DIO U 1..4 I Power Converter Master Optical Trigger Courtesy A. Luedeke, PSI

9. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Enhancements to the SLS PS Design Diamond Light Source exploits the following capabilities of the SLS system Works with any PWM power converter so use commercial units (OCEM, Bruker) One controller can drive multiple, load-sharing AC converter power modules So use multiples of standard units to customize, e.g. 4 x 25 A modules for one 100 A supply Add an extra module to take up load if one fails Modules are hot-swappable Reliability, with minimal downtime from PS

10. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Beam Position Monitoring requirements

11. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Beam Position Monitors Stripline BPMs in the injector and linac (existing) and in the LTU Differencing large numbers Mechanical precision Fabrication by printing electrodes on ceramic tubes Drift in electronics Digital signal processing Cavity BPMs in the undulator, LTU launch Signal inherently zero at geometric center C-band (inexpensive) signal needs to be mixed down in the tunnel

12. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Stripline versus Cavity BPM Signals P f 700 MHz 500 MHz BP filter ADC x4 119 MHz Clock 24 th harmonic Digital processing RF in Control system /4 Stripline Mixer LO sync’ed to RF IF noise (resolution) minimized by removing analog devices in front of ADC that cause attenuation drift minimized by removing active devices in front of ADC noise (resolution) minimized by removing analog devices in front of ADC that cause attenuation drift minimized by removing active devices in front of ADC C-band cavity Dipole mode coupler ~5 GHz

13. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Simplistic View of Digital BPMs Is the purely digital approach the best way to go? Must always maximize signal to noise for best resolution So minimize any cause of attenuation: couplers, hybrids, active devices etc. This also eliminates drift which causes offsets Other approaches also try to do this: e.g. AM to PM conversion with a hybrid and then digitize Might as well digitize first, eliminate the middle men, and do the conversions digitally Ultimately left with calibrating the drift in the BPM cables, because ADCs are now very stable.

14. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Linac stripline BPMs Need to replace old BPM electronics Commercially available processing units look promising Beam testing of module (on order) can begin soon http://www.i-tech.si

15. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Analysis of Test Signals in the “Libera” module – S. Smith Measured signal to noise ratio implies resolution of 7  m in a 10 mm radius BPM Identified fixable artifacts in data processing

16. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Pros and Cons of the Libera concept Complete, integrated commercial package which comes close to requirements RF processing, digitization, calibration, control software and feedback DSP all in one box Makes it hard for us get inside and tweak it Access to fast signals for feedback systems Difficult to provide timestamps and interrupts in their O/S Might be better to separate out the functions into different modules

17. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Fabricating a Digital BPM processor out of commercially available modules – Till Straumann RF filter, local oscillator and mixer stage VME based ADC board e.g. Joerger, Echotek handle 8 channels IOC Calculates signal amplitude & beam position, tmit. interfaces to EPICS, procedures for calibration, process feedback algorithm

18. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Signal losses in long BPM cables versus placing electronics in the tunnel We are choosing a high frequency component of the BPM signal to maximize amplitude But this is rapidly attenuated in long cable runs Can down-convert next to the BPM with a local oscillator and a mixer Unacceptable to put electronics in the linac tunnel, pay for better cables But may be acceptable to put down-converter electronics in the undulator and LTU tunnels Highest resolution required there

19. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Timing system requirements Synchronization of fiducials in low-level RF with distribution of triggers in the control system 1/360 s Linac 476 MHz Main Drive Line Sector feed Fiducial detector Master Pattern Generator SLC Control System Event Generator 360 Hz Triggers 8.4 ns±10 ps 128-bit word beam codes 119 MHz 360 Hz fiducials phase locked to low level RF

20. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Digital distribution of SLAC timing 10 GBit ethernet hardware but not ethernet protocol. RF master oscillator 476 MHz MDL Divide by 4 Fiducial detector Event generator EVG VME module Fan out 8 ch Event receiver EVR VME module fiber 8.4 ns 16 bit word 8.4 ns Clock 119 MHz FPGA Triggers 3 ps stability Triggers Technology developed at SLS Commercialized, refined, adopted at Diamond Optional vernier module

21. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 3 Levels in the Timing System “coarse” triggers at 360 Hz with 8.4 ns delay step size and 10 ps jitter Gated data acquisition (BPMs) Pulsed devices (klystrons) Phase lock of the low-level RF 0.05 S-band (50 fs) phase stability Timing measurement of the pump-probe laser w.r.t. electron beam in the undulator 10 fs resolution

22. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 LCLS Machine Stability Tolerance Budget X-band X-X-X-X- From P. Emma: RMS tolerance budget for <12% rms peak-current jitter or <0.1% rms final e− energy jitter. All tolerances are rms levels and the voltage and phase tolerances per klystron for L2 and L3 are  Nk larger, assuming uncorrelated errors, where Nk is the number of klystrons per linac. 125 fs tolerance on X-band system

23. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Beam based feedback will stabilize RF  A Against drift and jitter up to ~10 Hz But no diagnostic to distinguish drift of X-band Linearization, higher-harmonic RF has the tightest tolerance No unique beam measurement Energy and Bunch Length Feedback Loops L0 L1 DL1 Spectr. BC1 BC2 L2L3 BSY 50B1 DL2 V rf (L0) Φ rf (L2) V rf (L1) Φ rf (L3) EEE Φ rf (L2) zz Φ rf (L1) zz E

24. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 CSR Single-shot Bunch Length Detector Off-axis synchrotron radiation Reflected through a port to: Fixed BW detector Autocorrelator Prototype at SPPS THz autocorrelator THz power detector B4 Bend Bunch Compressor Chicane CSR Vacuum port with reflecting foil

25. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 End of presentation! Additional backup material follows

26. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Linac type stripline BPMs LCLS range Resolution achievable with existing processor New BPM processor design challenges: large dynamic range Low noise, high gain 20 ps timing jitter limit

27. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Cavity beam position monitors for the undulator and LTU Coordinate measuring machine verification of cavity interior X-band cavity shown Dipole-mode couplers X-band cavity shown Dipole-mode couplers R&D at SLAC – S. Smith X-band cavity shown Dipole-mode couplers X-band cavity shown Dipole-mode couplers NLC studies of cavity BPMs, S. Smith et al

28. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 C-band beam tests of the cavity BPM – S. Smith 25  m 200 nm Raw digitizer records from beam measurements at ATF cavity BPM signal versus predicted position at bunch charge 1.6 nC plot of residual deviation from linear response << 1  m LCLS resolution requirement plot of residual deviation from linear response << 1  m LCLS resolution requirement C-band chosen for compatibility with wireless communications technology

29. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Synchronization of the Laser timing Jitter in the laser timing effects Electro optic bunch timing measurement Pump-probe timing for the users Enhancement schemes using short pulse lasers Jitter in the laser timing effects Electro optic bunch timing measurement Pump-probe timing for the users Enhancement schemes using short pulse lasers

30. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 SPPS Laser Phase Noise Measurements – R. Akre 476 MHz M.O. x6 2856 MHz to linac MDL 3 km fiber ~1 km VCO Ti:Sa laser osc diode EO scope Phase detector 2856 MHz

31. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Electro-Optical Sampling at SPPS – A. Cavalieri et al. Single-Shot <300 fs 170 fs rms Timing Jitter ErEr Line image camera polarizer analyzer Pol. Laser pulse Electron bunch EO crystal Bunch length scan

32. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Antidamp Damp Gain bandwidth for different loop delays - L. Hendrickson Closed Loop Response of Orbit Feedback

33. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Control of Digital Power Supplies Andreas Lüdeke Swiss Light Source / PSI 20 May 2003 EPICS Collaboration Meeting

34. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 PSI Digital Power Supplies ADC/DAC Card DSP Controller DCC T 0..6 Slaves Magne t PWM Signal Fast Optical Link (5 MHz) DIO U 1..4 I Power Converter Master Optical Trigger Andreas Lüdeke

35. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Why use Digital Power Supplies? Single source of drifts: ADC voltage reference All PS at the SLS proved to have excellent stability Flexibility of the power supplies Regulation loop can be adapted to load Easy to add new power supply features on DSP Good reproducibility, reliability PWM is digital, modern DCCT will be digital Why not? Andreas Lüdeke

36. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Hardware Overview Linux PC Consoles IOCEVRCarrier IP Orbit DSP Timing Trans.Mod. VME T.Mod Power Supply Controller Parallel fast access (10k frames per sec) IOC  IP DSP  IP … Andreas Lüdeke

37. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Power Supply Hardware DSP Controller Card Euro card size Shark DSP Shark links on backplane ADC/DAC card 2 ADC, 16 Bit, 50 kHz 4 ADC, 12 Bit 2 DAC for debugging Andreas Lüdeke

38. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Fast and precise ADC 0200400600800100012001400160018002000 4.7888 4.7889 4.789 4.7891 4.7892 4.7893 4.7894 4.7895 - 10 µV + 20 µV - 40 µV 33 min t [s] U ADC [V] Umax Umin 1 kHz Filter 10 µV  1 ppm  20 th Bit 600 µV Andreas Lüdeke

39. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 VME Hardware Industry Pack Carrier VME64x 4 slot boards “off-the-shelf”: Greenspring Vipc664 Hytec 8002 VME64x Transition module for 8 power supplies Industry Pack Module for 2 power supplies Andreas Lüdeke

40. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 DSP Software Local intelligence: 50 kHz pulse width modulation loop Sophisticated alarms, like change in load resistance Triggered current waveform (DSP ramp) Scaleable, arbitrary waveform 16000 times 80 µsec steps  > 1 second waveform The same DSP program for all PS Locally stored parameter settings for each PS Andreas Lüdeke

41. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 EPICS device/driver Carrier board independent by use of drvIpac Read and write 256 power supply registers DSP waveform and program downloads Softramps: synchronised current waveforms Arbitrary clock rate (<1kHz) for 8000 setpoints Synchronised by timing system Diagnostic records Statistics of optical fibre link and IP failures Andreas Lüdeke

42. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 EPICS database One template for 500 power supplies Each power supply supports Download and save of DSP programs, parameter sets, DSP ID current waveform: download, scaling, offset, length, … reading max. and min. current from PS reading actual magnet resistance from controller... Magnet cycling configurable for each PS Detailed fault diagnostic for PS, link and driver Andreas Lüdeke

43. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Software Management DSP software is documented by Excel sheets Script transforms sheets into a C include file Easy upgrade of the driver for new PS functions Identical DSP and EPICS software for all PS Configuration by parameter set Andreas Lüdeke

44. Patrick Krejcik LCLS FACpkr@slac.stanford.edu October 12-13, 2004 Outlook PSI type digital PS are “en vogue” Each manufacturer can get a PSI licence Diamond will use exclusively digital PS for magnets Soleil is evaluating the PSI digital PS Industry Pack module can be used on CPCI Driver source can be reused for Tango Customized DSP programs For specific application To drive several PS with one DSP card Andreas Lüdeke