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Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 491 - Senior Design I Lecture 12 - Metastability.

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Presentation on theme: "Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 491 - Senior Design I Lecture 12 - Metastability."— Presentation transcript:

1 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 491 - Senior Design I Lecture 12 - Metastability Fall 2007 Homework due Friday 10/3: Metastability problem, p. 18

2 ECE 491 Fall 2006Lecture 12 - Metastability2 Where we are  Last Time:  Data Communications 2 Asynchronous Serial Receiver Transmission codes for Clock Recovery (Manchester Codes)  Today:  Synchronizers & Metastability

3 ECE 491 Fall 2006Lecture 12 - Metastability3 Review - Synchronizers  Key idea: make sure inputs don’t change at a “bad time” in sequential circuits in1 in2 in3 00 1001 in1’ in1 0110 clk in1 NS 11 transient

4 ECE 491 Fall 2006Lecture 12 - Metastability4 Review - Synchronizers  Add a D Flip-Flop on each asynchronous input  Synchronize each input only once  Q: What happens when set up & hold time violated? DQ clk in2_a in2_s DQ in1_a in1_s in1_a CLK in1_s in2_a in1_s

5 ECE 491 Fall 2006Lecture 12 - Metastability5 Review - Flip-Flop Timing Window  Input must be stable:  Setup time t setup before edge  Hold time t h after edge  Asynchronous inputs can violate this! D Q clk t setup thth CLK t CQ What happens here? in1_s in1_a

6 ECE 491 Fall 2006Lecture 12 - Metastability6 Metastability When bad things happen to good synchronizers Q: What happens when t su / t h constraints violated? A: It depends, but there are three scenarios 1.Circuit correctly records new D value 1.Circuit retains old D value for an extra cycle 3.Metastability - “stuck” between legal 0 and 1 until it “resolves” CLK D Q1 Q2 Q3 t su thth t clk-q Resolution Time t r

7 ECE 491 Fall 2006Lecture 12 - Metastability7 What Metastability Looks Like Image Source: www.fpga-faq.com

8 ECE 491 Fall 2006Lecture 12 - Metastability8 Metastability  Two stable states  V o1 =L, V o2 =H  V o1 =H, V o2 =L  One metastable state  V o1 = V o2  Ugly characteristic: unbounded recovery time t r Graphic source: J. Rabaey, Digital Integrated Circuits, © Prentice-Hall, 1996 Metastable point

9 ECE 491 Fall 2006Lecture 12 - Metastability9 Metastability - “Ball on the Hill” Analogy  Sides of hill = stable states  Top of hill = metastable state  Gravity = gain of inverters  Any small “push” (e.g., noise) will move the ball off the hill and into a stable state

10 ECE 491 Fall 2006Lecture 12 - Metastability10 Metastability - Bad News / Good News  Bad news  Metastability is unavoidable  Recovery time is theoretically unbounded  Good news  Can empirically measure recovery times  Can use statistics from recovery times to make failure probability arbitrarily small  Most FPGAs are highly resistant to metastability

11 ECE 491 Fall 2006Lecture 12 - Metastability11 Measuring Metastability Characteristics  Intentionally cause metastability many times  Measure recovery for each occurrence  Fit recovery times to exponential function t clk-q Number Of Occurrences Recovery Time

12 ECE 491 Fall 2006Lecture 12 - Metastability12 Designing with Metastability  A synchronizer design at a given clock period provides a fixed amount of resolution time tr  Definition: a synchronization failure occurs when actual recovery time t r-actual > t r-available  For a given flip-flop, the mean time between failure (MTBF) is given by the formula f clk - System clock freq. a - asynchronous input rate of change.  - empirically derived constant T o - empirically derived constant t r - time available for resolution

13 ECE 491 Fall 2006Lecture 12 - Metastability13 Determining Resolution Time t r  Time available for metastability resolution t r = t clk - t setup - t prop Comb. Logic D Q D Q clk t prop t su

14 ECE 491 Fall 2006Lecture 12 - Metastability14 Resolution Time Example  Suppose that  f clk = 100MHz (t clk = 10ns)  a = 1MHz  t prop = 6.7ns  t setup = 1ns  Calculate t r :  t r = t clk - t setup - t prop  t r = 10ns - 6.7ns -1ns = 2.3ns Comb. Logic D Q D Q clk t prop =6.7ns t su =1ns

15 ECE 491 Fall 2006Lecture 12 - Metastability15 MTBF Calculation Example  “Typical” values for a 0.25µm ASIC library flip-flop   = 0.31ns  T o = 9.6as “as” = 10 -18 s  t r = 2.3ns  MTBF = 20.1 days - unacceptable!

16 ECE 491 Fall 2006Lecture 12 - Metastability16 What happens if we halve f clk ?  Suppose that  f clk = 50MHz (t clk = 20ns)  a = 1MHz  t prop = 6.7ns  t setup = 1ns  Calculate t r and MTBF:  t r = t clk - t setup - t prop  t r = 20ns - 6.7ns -1ns = 12.3ns  MTBF = 5.7 X 10 28 seconds = 1.8 X 10 21 years

17 ECE 491 Fall 2006Lecture 12 - Metastability17 Alternative: Dual-Stage Synchronizer  Increased value for t r : t r = t clk - t su - t pr t r = 10ns - 1ns = 9ns Comb. Logic D Q D Q clk t prop t su D Q

18 ECE 491 Fall 2006Lecture 12 - Metastability18 Dual-Stage MTBF Calculation  “Typical” values for a 0.25µm ASIC library flip-flop   = 0.31ns  T o = 9.6as “as” = 10 -18 s  t r = 9ns  Other timing information:  f = 100 MHz  a = 1 MHz  Homework:  MTBF = ?  How much better is this than the single-stage synchronizer? Answer: 4.23 X 10 15 s = 8.05 X 10 9 years

19 ECE 491 Fall 2006Lecture 12 - Metastability19 Other Synchronizer Alternatives  Metastability-hardened SYNC flip-flops  Multiple-Stage Synchronizers  Reduced-Clock Synchronizers

20 ECE 491 Fall 2006Lecture 12 - Metastability20 Reality Check: What about FPGAs?  Metastability info in FPGAs is scarce  One refrerence: Peter Alfke, “Metastability Delay and Mean Time Between Failures in Virtex-II Pro FFs”, October 2002.  Some statistical measurements for Virtex-II Pro FPGAs  Major conclusion: Metastability issues are not much of a problem

21 ECE 491 Fall 2006Lecture 12 - Metastability21 MTBF Calculation Example - Virtex II Pro  Values from a Xilinx Technical note:   = 0.02ns - 0.05ps (assume 0.05ps)  T o = not given, but assume = 9.6as “as” = 10 -18 s  t r = 2.3ns  MTBF = 9.89 X 10 22 seconds = 7,53 X 10 16 years - not to worry!

22 ECE 491 Fall 2006Lecture 12 - Metastability22 What to Do About Metastability  Start with simple synchronizer (single flip-flop)  Calculate MTBF for your system  Decide if it's acceptable  If not, use a different design  OR different design:  Two-stage flip-flop  Reduced-clock synchronizers

23 ECE 491 Fall 2006Lecture 12 - Metastability23 Coming Up  Detailed Design  Handshaking  Manchester Transmitter / Receiver  Ethernet

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