1. Logic Design Review – 3 Basic Sequential Circuits Lecture L14.3 Verilog

2. Basic Sequential Circuits Latches Flip-Flops Registers Counters Shift Registers Datapaths State Machines

3. R-S Latch R S Q Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

4. R-S Latch R S Q Active HIGH module RSlatch ( Q,R,S ); input R ; wire R ; input S ; wire S ; output Q ; reg Q ; always @(R or S) begin if(S == 1 && R == 0) Q = 1; else if(S == 0 && R == 1) Q = 0; end endmodule

5. R-S Latch -- Active High

6. R-S Latch R S Q Active LOW module RSlatch ( Q,R,S ); input R ; wire R ; input S ; wire S ; output Q ; reg Q ; always @(R or S) begin if(S == 0 && R == 1) Q = 1; else if(S == 1 && R == 0) Q = 0; end endmodule

7. R-S Latch -- Active Low

8. Note that this is different from the "textbook" RS latch module RSlatchNOR ( Q,R,S ); input R ; wire R ; input S ; wire S ; output Q ; wire Q ; wire F1, F2; nor #10 (F1,F2,R); nor #10 (F2,F1,S); assign Q = F1; endmodule 10ns propagation delay

9. R S Q 0 0 Q 0 store 0 1 1 set 1 0 0 reset 1 1 0 disallowed

10. How can you make this R-S latch from gates? R-S Latch R S Q Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

11. R S Q Q 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 0 0 1 1 R-S Latch R S Q Q is set to 1 when S is asserted (1), and remains unchanged when S is disasserted (0). Q is reset to 0 when R is asserted (1), and remains unchanged when R is disasserted (0). R SQ 00011110 0 1 Q = ~R & Q | ~R & S | S & Q 11 1 1 store set reset store

12. R S Q Q 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 0 0 1 1 Q = ~R & Q | ~R & S | S & Q store set reset store R-S Latch R S Q RS Latch

13. module RSlatchGates ( Q,R,S ); input R ; wire R ; input S ; wire S ; output Q ; wire Q ; assign #10 Q = ~R & Q | ~R & S | S & Q; endmodule

15. D Latch D EN Q Q follows D when EN is high, and remains unchanged when EN is low..

16. D Latch D EN Q module Dlatch ( Q,EN,D ); input EN ; wire EN ; input D ; wire D ; output Q ; reg Q ; always @(D or EN) if(EN == 1) Q = D; endmodule

17. D Latch

18. Basic Sequential Circuits Latches Flip-Flops Registers Counters Shift Registers Datapaths State Machines

19. D Flip-Flop 0 0 1 1 1 0 X 0 Q 0 !Q 0 D clk Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered always @(posedge clk) Q <= D; Behavior clk D Q !Q

20. clk D Q !Q module DFF (D, clk, Q, notQ ); input clk ; wire clk ; input D ; wire D ; output Q ; reg Q ; output notQ ; wire notQ ; always @(posedge clk) Q <= D; assign notQ = ~Q; endmodule DFF.v Note non-blocking assignment

21. D Flip-Flop

22. module DFFclr (D, clk, clr, Q, notQ ); input clk ; wire clk ; input clr ; wire clr ; input D ; wire D ; output Q ; reg Q ; output notQ ; wire notQ ; always @(posedge clk or posedge clr) if(clr == 1) Q <= 0; else Q <= D; assign notQ = ~Q; endmodule DFFclr.v Asynchronous clear

23. D Flip-Flop with Asynchronous Clear

24. Basic Sequential Circuits Latches Flip-Flops Registers Counters Shift Registers Datapaths State Machines

25. A 1-Bit Register Behavior always @(posedge clk) if(LOAD == 1) Q0 <= INP0;

26. A 4-Bit Register

27. // An n-bit register with asynchronous clear and load module register(clk,clr,load,d,q); parameter n = 8; input [n-1:0] d; input clk,clr,load; output [n-1:0] q; reg [n-1:0] q; always @(posedge clk or posedge clr) if(clr == 1) q <= 0; else if(load) q <= d; endmodule A Generic Register

29. Basic Sequential Circuits Latches Flip-Flops Registers Counters Shift Registers Datapaths State Machines

30. 3-Bit Counter always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 0; else Q <= Q + 1; end Behavior count3 clr clk Q(2 downto 0)

31. module counter3 (clk, clr, Q ); input clr ; wire clr ; input clk ; wire clk ; output [2:0] Q ; reg [2:0] Q ; // 3-bit counter always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 0; else Q <= Q + 1; end endmodule counter3.v Asynchronous clear Output count increments on rising edge of clk

32. counter3 Simulation

33. Clock Divider Clk4 = 4 MHz clock Q1 Q0 1.0 MHz Q20.5 MHz Q30.25 MHz 2.0 MHz Clock4.0 MHz

34. Basic Sequential Circuits Latches Flip-Flops Registers Counters Shift Registers Datapaths State Machines

35. 4-Bit Shift Register

36. shift4.v module ShiftReg(clk,clr,data_in,Q); input clk; input clr; input data_in; output [3:0] Q; reg [3:0] Q; // 4-bit Shift Register always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= data_in; Q[2:0] <= Q[3:1]; end endmodule Note non-blocking assignment

37. shift4 simulation

38. Ring Counter

39. ring4.v module ring4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Ring Counter always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[0]; Q[2:0] <= Q[3:1]; end endmodule

40. ring4 simulation

41. Johnson Counter

42. module johnson4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Johnson Counter always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= ~Q[0]; Q[2:0] <= Q[3:1]; end endmodule johnson4.v

43. Johnson Counter

44. A Random Number Generator

45. Q3 Q2 Q1 Q0 0 0 0 1 1 1 0 0 0 8 1 1 0 0 C 1 1 1 0 E 1 1 1 1 F 0 1 1 1 7 1 0 1 1 B 0 1 0 1 5 Q3 Q2 Q1 Q0 1 0 1 0 A 1 1 0 1 D 0 1 1 0 6 0 0 1 1 3 1 0 0 1 9 0 1 0 0 4 0 0 1 0 2 0 0 0 1 1

46. module rand4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Random number generator always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[3] ^ Q[0]; Q[2:0] <= Q[3:1]; end endmodule rand4.v

47. A Random Number Generator

48. clk inp Q2 Q0 Q1 outp Clock Pulse

49. module clk_pulse(clk,clr,inp,outp); input clk; input clr; input inp; output outp; wire outp; reg [2:0] Q; // clock pulse generator always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[2] <= inp; Q[1:0] <= Q[2:1]; end assign outp = Q[2] & Q[1] & ~Q[0]; endmodule clk_pulse.v

50. clk inp Q2 Q0 Q1 outp

51. Basic Sequential Circuits Latches Flip-Flops Registers Counters Shift Registers Datapaths State Machines

52. Lab 8 unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1);}

53. Basic Sequential Circuits Latches Flip-Flops Registers Counters Shift Registers Datapaths State Machines

54. A canonical sequential network

55. A Mealy state machine

56. A Moore state machine

57. SQRTctl

58. Lab 8

59. A Moore state machine

60. // Square root control module SQRTctrl(Clk, Clear, lteflg, strt, ald, sqld, dld, outld); input Clk, Clear, lteflg, strt; output ald, sqld, dld, outld; reg ald, sqld, dld, outld; reg[1:0] present_state, next_state; parameterstart = 2'b00, test = 2'b01, update = 2'b10, done = 2'b11; // State register always @(posedge Clk or posedge Clear) begin if (Clear == 1) present_state <= start; else present_state <= next_state; end

61. A Moore state machine

62. // C1: next state always @(present_state or start or lteflg) begin case(present_state) strt:if(strt == 1) next_state <= test; else next_state <=start; test:if(lteflg == 1) next_state <= update; else next_state <= done; update:next_state <= test; done: next_state <= done; default next_state <= start; endcase end

63. A Moore state machine

64. // C2: outputs always @(present_state) begin case(present_state) strt: begin ald = 1; sqld = 0; dld = 0; outld = 0; end test: begin ald = 0; sqld = 0; dld = 0; outld = 0; end update: begin ald = 0; sqld = 1; dld = 1; outld = 0; end done: begin ald = 0; sqld = 0; dld = 0; outld = 1; end default begin ald = 0; sqld = 0; dld = 0; outld = 0; end endcase end endmodule

65. Lab 8