1. Supply Voltage Degradation Aware Analytical Placement Andrew B. Kahng, Bao Liu and Qinke Wang UCSD CSE Department {abk, bliu, qiwang}@cs.ucsd.edu

2. 2 Outline Introduction –Motivation –Related work –Our work –Problem formulation Analysis and Observations Voltage Degradation Aware Placement Experiments Conclusions

3. 3 Motivation Increasingly significant voltage degradation along power networks in nanometer VLSI designs –shrinking layout feature sizes –increasing device density Logic malfunction Performance degradation –a 10% voltage drop could be responsible for 10% transistor performance degradation, and the effect is super-linear

4. 4 Related Work Techniques to reduce supply voltage degradation –wiresizing and edge augmentation –decoupling capacitor insertion –circuit de-tuning Placement and floorplan related techniques –local placement adjustment to allocate whitespace for decoupling capacitor insertion –allocation of power pads: more pads close to current drain hot spots –a floorplan objective for power network construction and supply voltage drop

5. 5 Summary of Existing Works Existing voltage drop reduction techniques focus on power supply network design Supply voltage degradation is also a function of supply currents of the circuit To the best of our knowledge, no analytical placement technique for voltage drop reduction is proposed

6. 6 Our Contributions We propose voltage degradation aware placement : relocating current drains for voltage drop reduction –represent voltage drop at a power node as a function of current drains and effective resistances –propose voltage drop as placement objective and integrate into an analytical placement framework –test our method on real designs with industry flow

7. 7 Model of Power Network Power network: modeled as a resistive netlist parallel metal wires at multiple layers metal layers connected at crossing points by vias Power pads on the top layer: modeled as DC voltage sources Active devices at the bottom layer: modeled as DC current drains –DC currents provide bounds for the actual AC currents

8. 8 Problem Formulation Given –a power supply network –worst-case current drains for each cell Find a placement to –reduce supply voltage drop –maintain comparable placement wirelength, area, and timing performance

9. 9 Outline Introduction Analysis and Observations –Analysis of voltage drop –Observations on voltage drop optimization –Computation of effective resistance Voltage Degradation Aware Placement Experiments Conclusions

10. 10 Analysis of Voltage Drop Voltage drop at an observation node t –each current drain I k has contribution to the voltage drop – : effective resistance for a current drain at node k to inject noise voltage at node t

11. 11 An Example Tree-Structure R2R2 R1R1 R3R3 s t I1I1 I2I2 I3I3 s : power pad t : observation node

12. 12 Objectives and Observations Given a power supply network, find a placement of current drains to minimize: –(a) voltage drop at a given observation node t –(b) average voltage drop of all nodes, or –(c) max voltage drop over all nodes (a) : greedy algorithm to locate largest current I k first to have smallest resistance (b) : greedy algorithm to locate largest current I k first to have smallest resistance (c) : NP-hard

13. 13 Effective Resistance (I) Direct modified nodal analysis –G: conductance matrix –matrix inversion O(n 3 ) –not feasible for practical power networks

14. 14 Effective Resistance (II) Random walk [Qian et al. DAC 2003] –resistance of the common part of two random walk paths that respectively start from nodes k and t and end at a power pad –a random walk path follows the corresponding current distribution probability: transition probability from node p to q on the random walk path is

15. 15 Effective Resistance (III) Better scalability and efficiency –contract power netlist by merging bottom-level wires and computing parallel resistances –compute effective resistance between observation nodes –apply bi-linear interpolation for supply voltage drop at any node

16. 16 Outline Introduction Analysis and Observations Voltage Degradation Aware Placement –Introduction of analytical placement –Voltage drop aware placement objectives –Implementation Experiments Conclusions

17. 17 Introduction of APlace (I) APlace: a general analytical placement framework High solution quality and strong extensibility Regard Global placement (NP-hard) as a Constrained Nonlinear Optimization Problem: – : density function that equals the total module area in a global cell g –D : average module area over all global cells

18. 18 Introduction of APlace (II) Apply smooth approximation of placement objectives: wirelength, density function, etc. Quadratic Penalty method –solve a sequence of unconstrained minimization problems for a sequence of µ ↓ 0 Conjugate Gradient solver –find an unconstrained minimum of a high-dimensional function –memory required is only linear in the problem size, which makes it adaptable to large-scale placement problems

19. 19 Outline Introduction Analysis and Observations Voltage Degradation Aware Placement –Introduction of analytical placement –Voltage drop aware placement objectives –Implementation Experiments Conclusions

20. 20 Average Voltage Drop N : the number of observation nodes : effective resistance for a current drain I v to generate a voltage-drop at node g –function of module v 's position during global placement –effective resistance at continuous positions are obtained using bi-linear interpolation –partial differentials are computed accordingly

21. 21 Worst Voltage Drop LOG-SUM-EXP function –smooth approximation of worst voltage drop –α: smoothing parameter and significance criterion for choosing power network nodes with large voltage drop to minimize –V worst : strictly convex, continuously differentiable and converges to the worst voltage drop as α converges to 0

22. 22 Outline Introduction Analysis and Observations Voltage Degradation Aware Placement –Introduction of analytical placement –Voltage drop aware placement objectives –Implementation Experiments Conclusions

23. 23 Implementation (I) Integrate voltage drop objectives into the analytical placement framework W v : weight of the voltage drop objective –computed according to the gradients derived from the wirelength and voltage drop terms –scaled voltage drop gradients comparable to wirelength gradients

24. 24 Implementation (II) β : voltage drop ratio –decide the ratio of voltage drop gradients to wirelength gradients –provide a knob to trade-off between voltage drop and wirelength objectives for the placer

25. 25 Outline Introduction Analysis and Observations Voltage Degradation Aware Placement Experiments –Experimental setup –Results Conclusions

26. 26 Experimental Setup Two industry circuits –TSMC library –six metal layers –power/ground ring at top 2 layers –4 power pads at the center of boundaries –AES: 5 stripes at M2 –PCI: 4 stripes at M6 and 5 large fixed macros Design#Cells#RowsTechUtilization AES1339712990nm0.6 PCI7128251180nm0.43

27. 27 Experimental Flow Design inputs: synthesized netlists, technology libraries, timing constraints and floorplans Power planning and routing, and pad placement in Cadence SoC Encounter Voltage drop aware and oblivious placements using our placer and wirelength-driven APlace Fast global and detail routing by Cadence TrialRoute Steady-state voltage-drop analysis by Cadence VoltageStorm IR-Drop Design

28. 28 Outline Introduction Analysis and Observations Voltage Degradation Aware Placement Experiments –Experimental setup –Results Conclusions

29. 29 Results (I): Worst Voltage Drop Results of worst voltage-drop aware placements with a variety of voltage drop ratios (β 's) (β)(β)

30. 30 Results (II): Average Voltage Drop Results of average voltage-drop aware placements with a variety of voltage drop ratios (β 's) (β)(β)

31. 31 Summary of Results Improvement –worst voltage drop: 22.7% and 19.0% –average voltage drop: 10.2% and 13.1% Impact on HPWL: -3.2% and -5.3% Worst voltage drop objective leads to better results than average voltage drop objective –large voltage drops are among the first to be reduced –benefit the average voltage drop more than trying to reduce all the voltage drops with same efforts

32. 32 HPWL vs. Voltage Drop HPWL, worst-case and average voltage-drop improvements as functions of voltage drop ratio for AES

33. 33 Conclusions We propose analytical placement for supply voltage drop reduction We integrate supply voltage drop objective into an analytical placement framework Our experimental results show on average 20.9% improvement of worst-case voltage drop and 11.7% improvement of average voltage drop with only 4.3% wirelength increase Ongoing research efforts: supply voltage drop aware timing-driven placement

34. 34 Thank You !