1. 1 1999 ©UCB CS 162 Computer Architecture Lecture 1 Instructor: L.N. Bhuyan www.cs.ucr.edu/~bhuyan/cs162

2. 2 1999 ©UCB Instructor Information Laxmi Narayan Bhuyan Office: SURGE 319 E-mail: bhuyan@cs.ucr.edubhuyan@cs.ucr.edu Tel: (909) 787-2347 Office Times: W, Th 2-3 pm

3. 3 1999 ©UCB Course Syllabus Advanced processor design: CPU pipelining, Datapath and Control Design, Data and Control Hazards: The topics will be covered from Chapter 6 of the text °Instruction level parallelism, Dynamic scheduling of instructions, Branch Prediction and Speculation – From reference book and papers °VLIW, Multithreading, and Network processor architectures – From papers ° Basic multiprocessor design: Shared memory and message passing; Network topologies. The topic will be covered from Chapter 9 of the text. Main Text: Patterson and Hennessy, Computer Organization and Design, Morgan Kaufman Publisher Reference: Hennessy and Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufman Publisher Laboratory Assignments: (1) Design of ILP-based processor using SimpleScalar (www.simplescalar.com) (2) Simulating Intel IXP 1200 network processor using SDK simulator (3) Performance measurement of IXP 1200-based router

4. 4 1999 ©UCB Course Details °Prerequisite: CS 161 with a grade C or better °Grading: Based on Curve Test1: 25 points Test 2: 30 points Lab: 30 points Project: 15 points

5. 5 1999 ©UCB Review of CS 161 What is a von-Neumann computer? => The Stored Program Concept – Sequential Execution of a program – instructions in binary for storing in memory °Design of an Instruction Set - RISC Vs. CISC, Examples °Design of CPU Datapath °CPU Control Design ( Hardwire vs. Microprogramming) °Memory Design ( Main memory, Cache Memory, Virtual memory ) °Input-Output

6. 6 1999 ©UCB MIPS ISA 1. all MIPS instructions are same length simplifies fetch and decode (steps 1,2) Intel 80x86 and IBM 360/370 instructions are variable length, 1-17 bytes 2. few instruction formats in MIPS source register fields are same place in all instructions can read two registers and decode instruction in the same cycle Explicit Load/Store instructions for memory-register operations

7. 7 1999 ©UCB Review of CPU Datapath Design Instruction operation consists of 5 parts, namely, Fetch (IF), Decode (ID), Execute (EX), Memory (DM), and Write-back (WB) stages Single Cycle Design – Big Cycle – CPI = 1 Problems: (1) Low frequency meaning less number of instructions executed per cycle (2) All instns take same one big cycle Multicycle Design – Small Cycle – CPI complex control design, but still manageable in hardware.

8. 8 1999 ©UCB Review: Datapath for MIPS Data Memory (Dmem) PCRegisters ALU Instruction Memory (Imem) Stage 1Stage 2Stage 3 Stage 4 Stage 5 IFtchDcdExecMemWB °Use datapath figure to represent stages ALU IM Reg DMReg

9. 9 1999 ©UCB Pipelined Execution IPC= 1 °To simplify pipeline, every instruction takes same number of steps, called stages °One clock cycle per stage IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB Program Flow Time

10. 10 1999 ©UCB ALU IM Reg DMReg IM Graphical Pipeline Representation I n s t r. O r d e r Time (clock cycles) Load Add Store Sub Or ALU IM Reg DMReg ALU IM Reg DMReg ALU Reg DMReg ALU IM Reg DMReg (right half highlighted means read, left half write)

11. 11 1999 ©UCB Example: Single-cycle vs. Pipelined ALU IM Reg DM Reg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg 2 4 6 8 10 12 14 16 18 20 time ALU IM Reg DM Reg ALU IM Reg 123123 123123

12. 12 1999 ©UCB Advanced Architectural Concepts °Can we achieve CPI 1?) State-of-the-Art Microprocessor °“Superscalar” execution or Instruction Level Parallelism (ILP) “Deeper Pipeline => Dynamic Branch Prediction => Speculation => Recovery °“Out-of-order” Execution => Instruction Window and Prefetch => Reorder Buffers °“VLIW” Ex: Intel/HP Titanium

13. 13 1999 ©UCB Instruction Level Parallelism (ILP) IPC > 1 IFtchDcdExecMemWB Mem Dcd ExecMem WB IFtchDcdExecMemWB IFtch Dcd Exec MemWB IFtch Dcd Exec Mem WB Program Flow ILP = 2 Time IFtch Dcd ExecWB IFetch EX: Pentium, SPARC, MIPS 10000, IBM Power PC

14. 14 1999 ©UCB Very Large Instruction Word (VLIW) IPC > 1 IFtchDcdExecMemWB Exec IFtchDcdExecMemWB Exec IFtch Dcd Exec Mem WB Program Flow EX: Itanium Time Exec