1. Noise Canceling in 1-D Data: Presentation #10 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 April 4 th, 2005 Chip Level Layout 3 Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

2. Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics (Done) To be done: –Layout (98%) –Spice simulation (85%)

3. Current Floorplan

4. Layer Masks - Poly

5. Layer Masks - Metal 1

6. Layer Masks – Metal 2

7. Layer Masks – Metal 3

8. Layer Masks – Metal 4

9. The Chip Dimensions –Width = 364.275µ –Height = 300.96µ Area = 109632.204µ² Transistor count = 25385 –NMOS: 11862 –PMOS: 13523 Density = 0.232 trans/µ² Aspect ratio = 1: 1.21 (dimensions from previous floorplan: W: 345.645µ H:354.195µ A: 122425.73µ²)

10. Floating Point Adder 1

11. Floating Point Adder 2

12. Floating Point Adder 3

13. Questions?