1. 048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion isaac@ee.technion.ac.il http://comnet.technion.ac.il/~isaac/ The Load-Balanced Router

2. Spring 2006048866 – Packet Switch Architectures2 Achieving 100% throughput 1. Switch model 2. Uniform traffic  Technique: Uniform schedule (easy) 3. Non-uniform traffic, but known traffic matrix  Technique: Non-uniform schedule (Birkhoff-von Neumann) 4. Unknown traffic matrix  Technique: Lyapunov functions (MWM) 5. Faster scheduling algorithms  Technique: Speedup (maximal matchings)  Technique: Memory and randomization (Tassiulas)  Technique: Twist architecture (buffered crossbar) 6. Accelerate scheduling algorithm  Technique: Pipelining  Technique: Envelopes  Technique: Slicing 7. No scheduling algorithm  Technique: Load-balanced router

3. Spring 2006048866 – Packet Switch Architectures3 The Arbitration Problem  A packet switch fabric is reconfigured for every packet transfer.  For example, at 160Gb/s, a new IP packet can arrive every 2ns.  The configuration is picked to maximize throughput and not waste capacity.  Known algorithms are probably too slow.

4. Spring 2006048866 – Packet Switch Architectures4 Approach  We know that a crossbar with VOQs, and uniform Bernoulli i.i.d. arrivals, gives 100% throughput for the following scheduling algorithms:  Pick a permutation uar from all permutations.  Pick a permutation uar from the set of size N in which each input-output pair (i,j) are connected exactly once in the set.  From the same set as above, repeatedly cycle through a fixed sequence of N different permutations.  Can we make non-uniform, bursty traffic uniform “enough” for the above to hold?

5. Spring 2006048866 – Packet Switch Architectures5 Outline  Basic idea of load-balancing  Packet mis-sequencing  An optical switch fabric

6. Spring 2006048866 – Packet Switch Architectures6 In Out R R R R R R Router capacity = NR Switch capacity = N 2 R 100% Throughput in a Mesh Fabric ? ? ? ? ? ? ? ? ? R R R R R R R R R R R R R

7. Spring 2006048866 – Packet Switch Architectures7 R In Out R R R R R R/N If Traffic Is Uniform R R

8. Spring 2006048866 – Packet Switch Architectures8 Real Traffic is Not Uniform R In Out R R R R R R/N R R R R R R R R R ?

9. Spring 2006048866 – Packet Switch Architectures9 Out R R R R/N Load-Balanced Switch Load-balancing stageForwarding stage In Out R R R R/N R R R 100% throughput for weakly mixing traffic (Valiant, C.-S. Chang)

10. Spring 2006048866 – Packet Switch Architectures10 Out R R R R/N In R R R R/N 1 1 2 2 3 3 Load-Balanced Switch

11. Spring 2006048866 – Packet Switch Architectures11 Out R R R R/N In R R R R/N 3 3 2 2 1 1 Load-Balanced Switch

12. Spring 2006048866 – Packet Switch Architectures12 Out R R R R/N In R R R R/N Intuition: 100% Throughput  Arrivals to second mesh:  Capacity of second mesh:  Second mesh: arrival rate < service rate [C.-S. Chang et al.]

13. Spring 2006048866 – Packet Switch Architectures13 Another way of thinking about it 1 N 1 N 1 NExternal Outputs Internal Inputs External Inputs Load-balancing cyclic shift Switching cyclic shift Load Balancing  First stage load-balances incoming packets  Second stage is a cyclic shift

14. Spring 2006048866 – Packet Switch Architectures14 Load-Balanced Switch External Outputs Internal Inputs 1 N External Inputs Load-balancing cyclic shift Switching cyclic shift 1 N 1 N 1 1 2 2

15. Spring 2006048866 – Packet Switch Architectures15 Load-Balanced Switch

16. Spring 2006048866 – Packet Switch Architectures16 Outline of Chang’s Proof

17. Spring 2006048866 – Packet Switch Architectures17 Outline  Basic idea of load-balancing  Packet mis-sequencing  An optical switch fabric

18. Spring 2006048866 – Packet Switch Architectures18 Out R R R R/N In R R R R/N 1 2 Packet Reordering

19. Spring 2006048866 – Packet Switch Architectures19 Out R R R R/N In R R R R/N 1 2 Bounding Delay Difference Between Middle Ports

20. Spring 2006048866 – Packet Switch Architectures20 Out R R R R/N In R R R R/N 1 2 3 1 2 UFS (Uniform Frame Spreading)

21. Spring 2006048866 – Packet Switch Architectures21 Out R R R R/N In R R R R/N 1 2 FOFF (Full Ordered Frames First)

22. Spring 2006048866 – Packet Switch Architectures22 FOFF (Full Ordered Frames First)  Input Algorithm  N FIFO queues corresponding to the N output flows  Spread each flow uniformly: if last packet was sent to middle port k, send next to k+1.  Every N time-slots, pick a flow: - If full frame exists, pick it and spread like UFS - Else if all frames are partial, pick one in round-robin order and send it 12 3 1 2 4 N

23. Spring 2006048866 – Packet Switch Architectures23 Out R R R R/N In R R R R/N 1 2 3 Bounding Reordering

24. Spring 2006048866 – Packet Switch Architectures24 FOFF  Output properties  N FIFO queues corresponding to the N middle ports  Buffer size less than N 2 packets  If there are N 2 packets, one of the head-of-line packets is in order 11 1 2 2 3 3 3 Output 4 N

25. Spring 2006048866 – Packet Switch Architectures25 FOFF Properties  Property 1: FOFF maintains packet order.  Property 2: Congestion buffers operate independently.  Property 3: FOFF has O(1) complexity.  Property 4: FOFF maintains an average packet delay within constant from ideal output-queued router.  Corollary: FOFF has 100% throughput for any adversarial traffic.

26. Spring 2006048866 – Packet Switch Architectures26 Outline  Basic idea of load-balancing  Packet mis-sequencing  An optical switch fabric

27. Spring 2006048866 – Packet Switch Architectures27 Out R R R R/N In R R R R/N One linecard In Out From Two Meshes to One Mesh

28. Spring 2006048866 – Packet Switch Architectures28 From Two Meshes to One Mesh First mesh In Out In Out In Out In Out One linecard Second mesh R R R R R

29. Spring 2006048866 – Packet Switch Architectures29 From Two Meshes to One Mesh Combined mesh In Out In Out In Out In Out 2R R

30. Spring 2006048866 – Packet Switch Architectures30 Many Fabric Options Options Space: Full uniform mesh Time: Round-robin crossbar Wavelength: Static WDM Any spreading device C 1, C 2, …, C N C1C1 C2C2 C3C3 CNCN In Out In Out In Out In Out N channels each at rate 2R/N One linecard

31. Spring 2006048866 – Packet Switch Architectures31 AWGR (Arrayed Waveguide Grating Router) A Passive Optical Component  Wavelength i on input port j goes to output port (i+j-1) mod N  Can shuffle information from different inputs  1,  2 …  N NxN AWGR Linecard 1 Linecard 2 Linecard N  1  2  N Linecard 1 Linecard 2 Linecard N

32. Spring 2006048866 – Packet Switch Architectures32 In Out In Out In Out In Out Static WDM Switching: Packaging AWGR Passive and Almost Zero Power A B C D A, B, C, D A, A, A, A B, B, B, B C, C, C, C D, D, D, D N WDM channels, each at rate 2R/N