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Nanotechnology: Spatial Computing Using Molecular Electronics Mihai Budiu joint work with Seth Copen Goldstein Dan Rosewater
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SSS April 20, 20012 Intersection of Three Areas Reconfigurable computing Nanotechnology Computer architecture
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SSS April 20, 20013 Prophecies, A Risky Endeavor I think there is a world market for maybe five computers. --- T. J. Watson 640K ought to be enough for everybody. --- Bill Gates There is no reason anyone would want a computer in their home. --- Ken Olson I will propose this semester. --- Anonymous There is not the slightest indication that nuclear energy will ever be obtainable. --- Albert Einstein
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SSS April 20, 20014 Moore’s Law
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SSS April 20, 20015 Moore’s Second Law Plant costMask cost generation X 1000$
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SSS April 20, 20016 Our Proposal Nanotechnology + cheap + high-density + low-power – unreliable Computer architecture + vast body of knowledge – expensive – high-power Reconfigurable Computing + defect tolerant + high performance – low density + + + + + + _ _ _ _
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SSS April 20, 20017 Paradigm Shift Executable Configuration Complex fixed chip + Program Dense, regular structure + Configuration
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SSS April 20, 20018 Outline Introduction Reconfigurable computing Nanotechnology Nano-architecture proposal Preliminary results Conclusions and Future Work
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SSS April 20, 20019 Reconfigurable Computing Back to ENIAC-style computing Synthesize one machine to solve one problem
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SSS April 20, 200110 Island-Style RC Architecture Universal gates and/or storage elements Interconnection network Programmable Switches
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SSS April 20, 200111 Switch controlled by a 1-bit RAM cell 00010001 Universal gate = RAM a0 a1 a0 a1 data a1 & a2 0 data in control Main RC Ingredient: RAM Cell
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SSS April 20, 200112 Place and Route int reverse(int x) { int k,r=0; for (k=0; k<64; k++) r |= x&1; x = x >> 1; r = r << 1; } int func(int* a,int *b) { int j,sum=0; for (j=0; *a>0; j++) sum+=reverse(*b
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SSS April 20, 200113 Kernel Speedup Using PipeRench 189.7 15.5 11.3 12.0 63.3 42.4 26.0 57.1 29.0 1 10 100 1000 ATR Cordic DCT DCT-2D FIR IDEA Nqueens Over PopCount Times Over 300Mhz UltraSparc-II
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SSS April 20, 200114 Defect Tolerance Despite having >70% of the chips defective, Teramac works flawlessly. Compilation has two phases: defect detection through self-testing placement for defect-avoidance
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SSS April 20, 200115 Outline Introduction Reconfigurable computing Nanotechnology Nano-architecture proposal Preliminary results Conclusions and Future work
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SSS April 20, 200116 Nanotechnology
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SSS April 20, 200117 Predicted Features Low Power: 10 10 gates use less than 2 W (compare to 3x10 7 transistors using 100 W in CMOS) Low cost (nanocents/gate) Small size (10 5 factor area gain) Nano-RAM cell In yellow: a CMOS RAM cell.
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SSS April 20, 200118 Nano-wires carbon nanotubues, Si, metal >2nm diameter, up to mm length excellent electrical properties A carbon nanotube: one molecule
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SSS April 20, 200119 Nano-switch
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SSS April 20, 200120 Nano-switch Between Nano-wires
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SSS April 20, 200121 Self-assembly
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SSS April 20, 200122 No Complex Irregular Structures
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SSS April 20, 200123 No Three-Terminal Devices
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SSS April 20, 200124 Diode-resistor Logic V DD Output Input 1 Input 2 A * B V AND B A A ^ B VVV AND A B A B A * B Nano-implementationElectrical equivalent
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SSS April 20, 200125 Nanoscale Latches D clock dataout Provide: signal restoration (amplification) clocking (synchronization) memory
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SSS April 20, 200126 High Defect Rate
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SSS April 20, 200127 Outline Introduction Reconfigurable computing Nanotechnology Nano-architecture proposal Preliminary results Conclusions and future work
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SSS April 20, 200128 The nanoBlock (3-in to 3-out Logic) +Vdd Gnd clk Inputs Outputs CMOS clk
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SSS April 20, 200129 Interconnecting nanoBlocks Switch block
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SSS April 20, 200130 Global View
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SSS April 20, 200131 Control cluster long-lines Many Clusters = nanoFabric
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SSS April 20, 200132 Compilation 1.Program 2.Split-phase Abstract Machines 3.Configurations placed independently 4.Placement on chip int reverse(int x) { int k,r=0; for (k=0; k > 1; r = r << 1; } } Computations & local storage Unknown latency ops.
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SSS April 20, 200133 Outline Introduction Reconfigurable Hardware Nanotechnology Nano-architecture proposal Preliminary results Conclusions and Future work
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SSS April 20, 200134 A graph of the whole program execution: A Limit Study of Performance Memory word Basic block Memory write Memory read Control-flow transfer
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SSS April 20, 200135 Area (10 6 units/cm 2 available)
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SSS April 20, 200136 Typical Program Graph (g721_e) Control flow transfer 100% memory cluster Memory reads 100% code cluster
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SSS April 20, 200137 Typical Program Graph (g721_e) Control flow transfer memory Memory reads code memcpy
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SSS April 20, 200138 Program Graph After Inlining memcpy memcpy
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SSS April 20, 200139 Application Slowdown
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SSS April 20, 200140 How Time Is Spent No caches: reads expensive No speculation
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SSS April 20, 200141 Future Work Better nano-devices More accurate hardware models in simulations Compilation technology
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SSS April 20, 200142 Conclusions Electronic nanotechnology promises to transcend the limitations of CMOS Nanofabrics are very well suited to reconfigurable computation 10 9 -gate designs can be managed through hierarchies of abstract machines
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