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Spring 07, Feb 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Consumption in a Memory Vishwani D. Agrawal.

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Presentation on theme: "Spring 07, Feb 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Consumption in a Memory Vishwani D. Agrawal."— Presentation transcript:

1 Spring 07, Feb 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Consumption in a Memory Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07

2 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)2 Memory Architecture Word 0 Word 1 Word 2 M bits Storage cell Word N-2 Word N-1 Input-Output (M bits) N words S0S0 S N-1 Word 0 Word 1 Word 2 M bits Storage cell Word N-2 Word N-1 Input-Output (M bits) N words S0S0 S N-1 A 0 A 1. A k-1 Decoder k address lines k = log 2 N

3 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)3 Memory Organization Sense amplifiers/drivers Column decoder A K A K-1 A L-1 Storage cell Word line Bit line Input-Output (M bits) A 0 A K-1 2 L-K M.2 K

4 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)4 An SRAM Cell bit VDD WL BL

5 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)5 Read Operation bit VDD WL BL 1. Precharge to VDD 2. WL = Logic 1 3. Sense amplifier converts BL swing to logic level

6 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)6 Precharge Circuit bit VDD WL BL Diff. sense ampl. VDD PC

7 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)7 Reading 1 from Cell Precharge time WL BL Sense ampl. output

8 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)8 Write Operation, bit = 1→ 0 bit VDD WL BL 0 1 1. Set BL = 0, BL = 1 2. WL = 1

9 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)9 Cell Array Power Management  Smaller transistors  Low supply voltage  Lower voltage swing (0.1V – 0.3V for SRAM)  Sense amplifier restores the full voltage swing for outside use.

10 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)10 Sense Amplifier bit SE Sense ampl. enable: Low when bit lines are precharged and equalized VDD Full voltage swing output

11 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)11 Block-Oriented Architecture  A single cell array may contain 64 Kbits to 256 Kbits.  Larger arrays become slow and consume more power.  Larger memories are block oriented.

12 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)12 Hierarchical Organization Global data bus Global amplifier/driver I/O Block 0 Block 1 Block P-1 Control circuitry Block selector Row addr. Column addr. Block addr.

13 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)13 Power Saving  Block-oriented memory  Lengths of local word and bit lines are kept small.  Block address is used to activate the addressed block.  Unaddressed blocks are put in power-saving mode:  sense amplifier and row/column decoders are disabled.  Power is maintained for data retention in cells.

14 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)14 Static Power 0.00.61.21.8 Supply voltage 1.3μ 1.1μ 900n 700n 500n 300n 100n 0.13μ CMOS 0.18μ CMOS 8-kbit SRAM 7x increase Leakage current (Amperes)

15 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)15 Adding Resistance in Leakage Path SRAM cell array SRAM cell array SRAM cell array GND VDD sleep Low-threshold transistor VSS.int VDD.int

16 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)16 Lowering Supply Voltage SRAM cell array SRAM cell array SRAM cell array GND VDD sleep VDDL= 100mV for 0.13μ CMOS Sleep = 1, data retention mode

17 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)17 Parallelization of Memories instr. A instr. C instr. E. f/2 Mem 1 instr. B instr. D instr. F. f/2 Mem 2 MUX f/2 01 Power = C’ f/2 V DD 2 C. Piguet, “Circuit and Logic Level Design,” pp. 124-125 in W. Nebel and J. Mermet (Eds.), Low Power Design in Deep Submocron Electronics, Springer, 1997.

18 Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)18 References  K. Itoh, VLSI Memory Chip Design, Springer- Verlag, 2001.  J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, Inc., 2003.

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