1. MS_uC / dnd / V08 6- 1 TIM - Timer Programming Microcontroller TIM - Timer Autumn term 2007 32K Byte Burst Flash 64K or 96K Byte SRAM 256K or 512K Byte Burst Flash OTP Mem UARTI2CSPI TIMRTC EXT. Bus GPIO USB 2.0FS CAN 2.0B Enet MAC PFQ BC DMA INTR Cntl ARM966 E CORE w/DSP 96 MHz CLK Cntl ADC LVD BOD PLL JTAGETM9 STR912FAW44

2. MS_uC / dnd / V08 6- 2 TIM - Timer Timer Features zFour 16 bit Timers, support: yTwo Input Captures yTwo Output Compares yPWM Out yPWM Input yOne Pulse Mode zTwo Clocks: External clocks, Internal PCLK z8 bit Prescaler zDMA support on Timer 0/1 Input Cap Reg 2 APB Bus Output Comp Reg 1 Ext CLK pin 16 Bit Counter/ Register Input Cap Reg 1 Edge Detect Circuit Interrupt - Overflow, OCMP, ICAP 8 Bit Prescaler PCLK Overflow Output Comp 1 Output Comp 2 Output Comp Reg 2 Edge Detect Circuit Latch 2Latch1ICAP1 ICAP2 OCMP1 OCMP2 Control Registers 16 Bit Prescaler SCU_SRx MCLK from SCU ®

3. MS_uC / dnd / V08 6- 3 TIM - Timer Timers Features z16 Bit Up Counter yProvide counter values for output compare and input capture zCounter Clock Control yInternal clock – PCLK with 8 bit prescaler yExternal clock – frequency must be less than ¼ of PLCK xOne external clock input for Timer 0 and 1, another for Timer 2 and 3 yMCLK clock (From SCU) xOne clock input for Timer 0 and 1, another for Timer 2 and 3 xEach clock has a 16 bit presacler xClock enable is defined in SCU_CLKCNTR register and Prescaler values are defined in SCU_SCR1 and 2 registers zInterrupt generation on timer events: yCounter Overflows, rolls over from FFFFh to 0000h yAfter a capture event yWhen compare register matches counter values ®

4. MS_uC / dnd / V08 6- 4 TIM - Timer Timer Modes zInput Capture Mode yTwo input pins, user programmable edge polarity yCapture counter values when input edge is detected yGenerate interrupt when enabled yCan measure input pulse width zOutput Compare Mode yTwo output compare pins, one for each compare register yCompare Register is compared with counter value yGenerate output signal/waveform on pin when a match occurred yUser programmable output signal level zOther Timer Modes yBased on the Input Capture and Output Compare logic xOne Pulse Mode xPWM Output Mode xPWM Input Mode ®

5. MS_uC / dnd / V08 6- 5 TIM - Timer Timer One Pulse Mode zGeneration of a pulse synchronized with an external event zOn Input Capture event yThe timer output pin is toggled to the OLVL2 level zOn Output compare event yThe timer waits for the next Input Capture event yThe timer output pin is toggled to the OLVL1 level yThe counter is reset to 0xFFFC IEDG1 = 1 OC1R = 0x2ED0 OLVL1 = 0 OLVL2 = 1 OLVL2 FFFC FFFD FFFE … 2ED02ED1 2ED2 2ED3FFFC Counter ICAP1 OCMP1 OLVL2 OLVL1 Compare 1 FFFC 2ED0 ®

6. MS_uC / dnd / V08 6- 6 TIM - Timer Timer PWM Output Mode zAutomatic generation of a Pulse Width Modulated signal zThe Output Compare 1 Register contains the length of the pulse zThe OLVL2 bit contains the level during the pulse zThe Output Compare 2 Register contains the period of the pulse zThe OLVL1 bit contains the level after the pulse OC2R = 0x34E2 OC1R = 0x2ED0 OLVL1= 0 OLVL2 = 1 zSimilar to the One Pulse Mode where the Input Capture event is replaced by the second Output Compare event OLVL2 FFFC FFFD FFFE 34E2 2ED02ED1 … FFFC Counter OCMP1 OLVL2 OLVL1 Compare 1Compare 2 34E2 Compare 2 34E22ED0 ®

7. MS_uC / dnd / V08 6- 7 TIM - Timer Timer PWM Input Mode (TIM_CR) zExternal pulse and period measurement of an external wave zThe First edge is configured through the IEDG1 bit zThe Second edge is configured through the IEDG2 bit zThe signal Full period is stored in the ICAP1 zThe Pulse length is stored in the ICAP2 zProgrammable first edge detection zInterrupt Generation IC2R = 0x34E2 IC1R = 0x2ED0 IEDG1 = 1 IEDG2 = 0 Period = ICAP1 Pulse Length = ICAP2 0000 0001 0002 34E2 2ED02ED1 … 0000 Counter ICAP1 Capture 2Capture 1 34E2 Capture 1 ®

8. MS_uC / dnd / V08 6- 8 TIM - Timer Timer Structure (1/2)

9. MS_uC / dnd / V08 6- 9 TIM - Timer Timer Structure (2/2)

10. MS_uC / dnd / V08 6- 10 TIM - Timer Presaler timer clock = Peripheral clock divided by Prescaler

11. MS_uC / dnd / V08 6- 11 TIM - Timer Timer Register Map

12. MS_uC / dnd / V08 6- 12 TIM - Timer Control Register 1

13. MS_uC / dnd / V08 6- 13 TIM - Timer Control Register 2

14. MS_uC / dnd / V08 6- 14 TIM - Timer ARM Peripheral Bus 0 access (APB0)

15. MS_uC / dnd / V08 6- 15 TIM - Timer GPIO Access through Memory

16. MS_uC / dnd / V08 6- 16 TIM - Timer Timer configuration

17. MS_uC / dnd / V08 6- 17 TIM - Timer Library sources

18. MS_uC / dnd / V08 6- 18 TIM - Timer Library examples