1. © Digital Integrated Circuits 2nd Inverter CMOS Inverter: Digital Workhorse  Best Figures of Merit in CMOS Family  Noise Immunity  Performance  Power/Buffer Ability  Utilization of Design Scale  Maxim  When in doubt – add an inverter!

2. © Digital Integrated Circuits 2nd Inverter CMOS Inverter Polysilicon In Out V DD GND PMOS 2 Metal 1 NMOS Contacts N Well

3. © Digital Integrated Circuits 2nd Inverter CMOS Inverter Load Characteristics

4. © Digital Integrated Circuits 2nd Inverter CMOS Inverter VTC

5. © Digital Integrated Circuits 2nd Inverter Low Frequency Switching Threshold vs. Transistor Ratio 10 0 1 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 M V (V) W p /W n

6. © Digital Integrated Circuits 2nd Inverter Inverter Gain

7. © Digital Integrated Circuits 2nd Inverter Gain as a function of VDD Gain=-1

8. © Digital Integrated Circuits 2nd Inverter Simulated VTC

9. © Digital Integrated Circuits 2nd Inverter Impact of Process Variations I 00.511.522.5 0 0.5 1 1.5 2 2.5 V in (V) V out (V) Fast PMOS Slow NMOS Fast NMOS Slow PMOS Typical

10. © Digital Integrated Circuits 2nd Inverter Impact of Process Variations II  Inverter Noise Margin  Directly limited by Process Variations  Also Function of Gain, Power Rail Noise, Temp 00.511.522.5 0 0.5 1 1.5 2 2.5 V in (V) V out (V)

11. © Digital Integrated Circuits 2nd Inverter Propagation Delay

12. © Digital Integrated Circuits 2nd Inverter CMOS Inverter: RC Transient Response Model  Assume Next Gate Switches at 50% swing  Total Delay from sum of sequential gate delays t pHL = f(R on.C L ) = 0.69 R on C L V out V R n R p V DD V Low-to-highHigh-to-low C L C L

13. © Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay RC Approximation

14. © Digital Integrated Circuits 2nd Inverter Transient Response (Equivalent R) t pLH t pHL

15. © Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay Hodges Approximation

16. © Digital Integrated Circuits 2nd Inverter Transient Model (Equivalent I)  Hodges Perscription for I avg :  Average of Initial and Final Currents over swing of interest  Easy since you know the voltages in CMOS: Init=0 or Vdd; Final= Vdd/2  Easy to add effects of other devices, capacitances and styles since current model

17. © Digital Integrated Circuits 2nd Inverter Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

18. © Digital Integrated Circuits 2nd Inverter Issues in Propagation Estimation  Critical Path??  Transitions are critical  Asymmetric transistor sizing may be good!  Dial in Noise/Level Shift/Favored Transition  Load  Interconnect  Terminal  Self-loading (non-linear)  Output Swing  Usually Vdd->Vdd/2 or GND->Vdd/2

19. © Digital Integrated Circuits 2nd Inverter NMOS/PMOS ratio tpLH tpHL tp  = W p /W n

20. © Digital Integrated Circuits 2nd Inverter Propagation Details  Most of Load is simple, but:  Non-linear Self Capacitance –Drain Junction and Sidewalls  Ratio Logic –Other current sources/sinks  Beware Body Effect  Source at different potential from back

21. © Digital Integrated Circuits 2nd Inverter Impact of Rise Time on Delay

22. © Digital Integrated Circuits 2nd Inverter Inverter Sizing

23. © Digital Integrated Circuits 2nd Inverter Inverter Chain CLCL If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out

24. © Digital Integrated Circuits 2nd Inverter Inverter Delay Minimum length devices, L=0.5  m Assume that for W P = 2.5W N = 2.5W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t pLH and fall t pHL delays Analyze as an RC network t pHL = (ln 2) R N C L t pLH = (ln 2) R P C L Delay (D): 2.5W W Load for the next stage:

25. © Digital Integrated Circuits 2nd Inverter Inverter with Load Load (C L ) Delay Assumptions: no load -> zero delay CLCL t p = k R W C L RWRW RWRW W unit = 1 k is a constant, equal to 0.69

26. © Digital Integrated Circuits 2nd Inverter Inverter with Load Load Delay C int CLCL Delay = kR W (C int + C L ) = kR W C int + kR W C L = kR W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load) C N = C unit C P = 2.5C unit 2.5W W

27. © Digital Integrated Circuits 2nd Inverter Delay Formula C int =  C gin with   1 f = C L /C gin - effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit

28. © Digital Integrated Circuits 2nd Inverter Apply to Inverter Chain CLCL InOut 12N t p = t p1 + t p2 + …+ t pN

29. © Digital Integrated Circuits 2nd Inverter Optimal Sizing for Given N Delay equation has N - 1 unknowns, C gin,2 – C gin,N Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors - each stage has the same effective fanout (C out /C in ) - each stage has the same delay

30. © Digital Integrated Circuits 2nd Inverter Optimum Delay and Number of Stages When each stage is sized by f and has same fanout f: Minimum path delay Effective fanout of each stage:

31. © Digital Integrated Circuits 2nd Inverter Example C L = 8 C 1 In Out C1C1 1ff2f2 C L /C 1 has to be evenly distributed across N = 3 stages:

32. © Digital Integrated Circuits 2nd Inverter Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f For  = 0, f = e, N = lnF

33. © Digital Integrated Circuits 2nd Inverter Optimum Effective Fanout f Optimum f for given process defined by  f opt = 3.6 for  =1

34. © Digital Integrated Circuits 2nd Inverter Impact of Self-Loading on tp No Self-Loading,  =0 With Self-Loading  =1

35. © Digital Integrated Circuits 2nd Inverter Buffer Design 1 1 1 1 8 64 4 2.8 8 16 22.6 Nft p 16465 2818 3415 42.815.3

36. © Digital Integrated Circuits 2nd Inverter Power Dissipation

37. © Digital Integrated Circuits 2nd Inverter Where Does Power Go in CMOS?

38. © Digital Integrated Circuits 2nd Inverter Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes!

39. © Digital Integrated Circuits 2nd Inverter Transistor Sizing for Minimum Energy  Goal: Minimize Energy of whole circuit  Design parameters: f and V DD  tp  tpref of circuit with f=1 and V DD =V ref

40. © Digital Integrated Circuits 2nd Inverter Transistor Sizing (2)  Performance Constraint (  =1)  Energy for single Transition

41. © Digital Integrated Circuits 2nd Inverter Transistor Sizing (3) F =1 2 5 10 20 V DD = f (f) E/E ref = f (f)

42. © Digital Integrated Circuits 2nd Inverter Short Circuit Currents

43. © Digital Integrated Circuits 2nd Inverter How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise, but can’t do this for cascade logic, so...

44. © Digital Integrated Circuits 2nd Inverter Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

45. © Digital Integrated Circuits 2nd Inverter Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!

46. © Digital Integrated Circuits 2nd Inverter Reverse-Biased Diode Leakage JS = 10-100 pA/  m2 at 25 deg C for 0.25  m CMOS JS doubles for every 9 deg C!

47. © Digital Integrated Circuits 2nd Inverter Subthreshold Leakage Component

48. © Digital Integrated Circuits 2nd Inverter Principles for Power Reduction  Prime choice: Reduce voltage!  Recent years have seen an acceleration in supply voltage reduction  Design at very low voltages still open question (0.6 … 0.9 V by 2010!)  Reduce switching activity  Reduce physical capacitance  Device Sizing: for F=20 –f opt (energy)=3.53, f opt (performance)=4.47