1. 7-Segment Display DIO1 Board

2. Digilab2 – DIO1 Boards Four 7-segment displays A0A1A2A3

3. DIO1 Board – Common Anodes A0 A1 A2 A3 AtoG(6:0) Pins

4. Multiplex displays 1 0 0 0 0 0 0 0 1 1 0

5. Multiplex displays 0 1 0 0 0 0 0 1 1 1 1

6. Multiplex displays 0 0 1 0 1 0 0 1 1 0 0

7. Multiplex displays 0 0 0 1 0 1 1 1 0 0 0

8. x7seg

9. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity x7seg is Port ( x : in std_logic_vector(15 downto 0); cclk, clr : in std_logic; AtoG : out std_logic_vector(6 downto 0); A : out std_logic_vector(3 downto 0) ); end x7seg; x7seg.vhd

10. architecture arch_x7seg of x7seg is signal digit : std_logic_vector(3 downto 0); signal count : std_logic_vector(1 downto 0); begin

11. ctr2bit: process(cclk,clr) begin if(clr = '1') then count <= "00"; elsif(cclk'event and cclk = '1') then count <= count + 1; end if; end process;

12. -- MUX4 with count select digit <= x(15 downto 12) when "00", x(11 downto 8) when "01", x(7 downto 4) when "10", x(3 downto 0) when others;

13. -- seg7dec with digit select AtoG <="1001111" when "0001",--1 "0010010" when "0010",--2 "0000110" when "0011",--3 "1001100" when "0100",--4 "0100100" when "0101",--5 "0100000" when "0110",--6 "0001111" when "0111",--7 "0000000" when "1000",--8 "0000100" when "1001",--9 "0001000" when "1010",--A "1100000" when "1011",--b "0110001" when "1100",--C "1000010" when "1101",--d "0110000" when "1110",--E "0111000" when "1111",--F "0000001" when others;--0

14. Acode: process(count) begin A '0'); A(conv_integer(count)) <= '1'; end process; end arch_x7seg; Example: count = 10 A(2) = 1 A(0) = A(1) = A(3) = 0 A(3:0) = 0100

15. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity x7seg_test is port ( mclk : in STD_LOGIC; bn : in STD_LOGIC; led: out std_logic; ldg : out STD_LOGIC; SW : in STD_LOGIC_VECTOR(1 to 8); AtoG : out STD_LOGIC_VECTOR(6 downto 0); A : out STD_LOGIC_VECTOR(3 downto 0) ); end x7seg_test; x7seg_test.vhd

16. architecture x7seg_test_arch of x7seg_test is -- System Library Components component IBUFG port ( I : in STD_LOGIC; O : out std_logic ); end component; component x7seg port ( x : in std_logic_vector(15 downto 0); cclk, clr : in std_logic; AtoG : out std_logic_vector(6 downto 0); A : out std_logic_vector(3 downto 0) ); end component;

17. signal clr, cclk, bnbuf: std_logic; signal clkdiv: std_logic_vector(23 downto 0); signal fix: std_logic_vector(7 downto 0); begin U00:IBUFG port map (I => bn, O => bnbuf); led <= bnbuf; ldg <= '1'; -- enable 74HC373 latch clr <= bnbuf;

18. -- Divide the master clock (50Mhz) down to a lower frequency. process (mclk) begin if mclk = '1' and mclk'event then clkdiv <= clkdiv + 1; end if; end process; cclk <= clkdiv(17);-- 190 Hz

19. U1: x7seg port map( x(7 downto 0) => SW, x(15 downto 8) => fix, cclk => cclk, clr => clr, AtoG => AtoG, A => A); fix <= "10100101";-- left 2 digits = A5 end x7seg_test_arch;