1. 331 W9.1Spring 2006 14:332:331 Computer Architecture and Assembly Language Spring 2006 Week 9 Building a Single-Cycle Datapath [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

2. 331 W9.2Spring 2006 Head’s Up  This week’s material l Building a MIPS single-cycle datapath -Reading assignment – PH 5.4

3. 331 W9.3Spring 2006 Review: Abstract Implementation View  Split memory (Harvard) model - single cycle operation  Simplified to contain only the instructions: memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j  Sequential components (PC, RegFile, Memory) are edge triggered l state elements are written on every clock cycle; if not, need explicit write control signal -write occurs only when both the write control is asserted and the clock edge occurs AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data

4. 331 W9.4Spring 2006 Example  Let’s modify the ISA and remove the ability to specify an offset for memory access instructions. Specifically, the load-store instructions would contain only two registers. In other words, all MIPS load-store instructions with offsets would become pseudoinstructions and would be implemented using two instructions: lw$t0, 104($t1) =>

5. 331 W9.5Spring 2006 Example cont’d Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead 18 17 1632 16-bit offset

6. 331 W9.6Spring 2006 Creating a Single Datapath from the Parts  Assemble the datapath segments from the last lecture, add control lines as needed, and design the control path  Fetch, decode and execute each instructions in one clock cycle – single cycle design l no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., why we have a separate Instruction Memory and Data Memory) l to share datapath elements between two different instruction classes will need multiplexors at the input of the shared elements with control lines to do the selection  Cycle time is determined by length of the longest path

7. 331 W9.7Spring 2006 Fetch, R, and Memory Access Portions Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 lw R R lw / sw

8. 331 W9.8Spring 2006 Multiplexor Insertion MemtoReg Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 ALUSrc

9. 331 W9.9Spring 2006 Adding the Branch Portion Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Read Address Instruction Memory Add PC 4 Shift left 2 Add PCSrc R lw / sw R lw Branch not taken, R, lw /sw

10. 331 W9.10Spring 2006 Adding the Control  Selecting the operations to perform (ALU, Register File and Memory read/write)  Controlling the flow of data (multiplexor inputs)  Information comes from the 32 bits of the instruction I-Type: oprsrt address offset 312520150 R-type: 3125201550 oprsrtrdfunctshamt 10  Observations l op field always in bits 31-26 l addr of two registers to be read are always specified by the rs and rt fields (bits 25-21 and 20-16) l addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions l base register for lw and sw always in rs (bits 25-21) l offset for beq, lw, and sw always in bits 15-0

11. 331 W9.11Spring 2006 (Almost) Complete Single Cycle Datapath Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr ALU ovf zero Data Memory Address Write Data Read Data MemWrite MemRead Register File Read Data 1 Read Data 2 RegWrite Sign Extend 1632 Shift left 2 Add RegDst 0 1 ALUSrc 0 1 MemtoReg 1 0 PCSrc 1 0 ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11]

12. 331 W9.12Spring 2006 ALU Control ALU control input ( Ainvert + Binvert + Operation ) Function 0000and 0001or 0010add 0110subtract 0111set on less than  ALU's operation based on instruction type and function code

13. 331 W9.13Spring 2006 ALU Control, Con’t  Controlling the ALU makes use of multiple levels of decoding l main control unit generates the ALUOp bits l ALU control unit generates ALU control inputs Instr opfunctALUOpdesired action ALU control input lwxxxxxx00add0010 swxxxxxx00add0010 beqxxxxxx01sub0110 add10000010add0010 subt10001010subtract0110 and10010010and0000 or10010110or0001 slt10101010slt0111

14. 331 W9.14Spring 2006 ALU Control Truth Table  Can make use of more don’t cares l since ALUOp does not use the encoding 11 l since F5 and F4 are always 10  Logic comes from the K-maps … F5F4F3F2F1F0ALUOp1ALUOp0Op3Op2Op1Op0 XXXXXX000010 XXXXXX10110 XX000010010 XX001010110 XX010010000 XX010110001 XX101010111 X X X X X X

15. 331 W9.15Spring 2006 (Almost) Complete Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

16. 331 W9.16Spring 2006 Instr[15 -11] Instr[20-16] Instr[25-21] R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Control Unit Instr[31-26] Branch

17. 331 W9.17Spring 2006 Instr[25-21] Instr[20-16] Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[15 -11] Control Unit Instr[31-26] Branch

18. 331 W9.18Spring 2006 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

19. 331 W9.19Spring 2006 Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

20. 331 W9.20Spring 2006 Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOp1ALUOp0 R-type 000000 1001X001X lw 100011 011110000 sw 101011 X1X0X1000 beq 000100 X0X0X01X1

21. 331 W9.21Spring 2006 Control Unit Logic  From the truth table can design the Main Control logic Instr[31] Instr[30] Instr[29] Instr[28] Instr[27] Instr[26] R-type lwswbeq RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0

22. 331 W9.22Spring 2006 Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28

23. 331 W9.23Spring 2006 Single Cycle Implementation Cycle Time  Unfortunately, though simple, the single cycle approach is not used because it is inefficient  Clock cycle must have the same length for every instruction  What is the longest path (slowest instruction)?

24. 331 W9.24Spring 2006 Instruction Critical Paths Instr.I MemReg RdALU OpD MemReg WrTotal R-type load store beq jump 21216 212218  Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except: l Instruction and Data Memory (2ns) l ALU and adders (2ns) l Register File access (reads or writes) (1ns) 21227 2125 22

25. 331 W9.25Spring 2006 Where We are Headed  Problems with single cycle datapath design l uses clock cycle inefficiently l and what if we had a more complicated instruction like floating point multiply? l wasteful of area  Another approach l use a “smaller” cycle time l have different instructions take different numbers of cycles l a “multicycle” datapath: Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout

26. 331 W9.26Spring 2006 Complete Datapath Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28

27. 331 W9.27Spring 2006 Example I: R instruction Control Signal SettingControl Signal Setting RegDstALUOp1 JumpAlUOp0 BranchMemWrite MemReadALUSrc MemtoRegRegWrite

28. 331 W9.28Spring 2006 Example I: lw instruction Control Signal SettingControl Signal Setting RegDstALUOp1 JumpAlUOp0 BranchMemWrite MemReadALUSrc MemtoRegRegWrite

29. 331 W9.29Spring 2006 Example I: sw instruction Control Signal SettingControl Signal Setting RegDstALUOp1 JumpAlUOp0 BranchMemWrite MemReadALUSrc MemtoRegRegWrite

30. 331 W9.30Spring 2006 Example I: beq instruction Control Signal SettingControl Signal Setting RegDstALUOp1 JumpAlUOp0 BranchMemWrite MemReadALUSrc MemtoRegRegWrite

31. 331 W9.31Spring 2006 Example II: cycle length  Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except: l Instruction and Data Memory (2ns) l ALU (2ns) l Register File access (reads or writes) (1ns) l Adder for PC+4 (5ns) l Adder for branch address computation (5ns)

32. 331 W9.32Spring 2006 Example III:  Describe the effect that a single stuck-at-0 fault (I.e., regardless of what it should be, the signal is always 0) would have on the multiplexors in the single-cycle datapath. Which instruction, if any, would still work? Consider each of the following faults separately: RegDst = 0, ALUSrc = 0, MemtoReg = 0, Zero = 0;

33. 331 W9.33Spring 2006 Example IV:  We wish to add the instruction addi to the single- cycle datapath. Add any necessary datapaths and control signals. Control Signal SettingControl Signal Setting RegDstALUOp1 JumpAlUOp0 BranchMemWrite MemReadALUSrc MemtoRegRegWrite

34. 331 W9.34Spring 2006 Complete Datapath Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28

35. 331 W9.35Spring 2006 Example V: add jal Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28 31 RegDst1 1 0 MemtoReg1

36. 331 W9.36Spring 2006 Example V: add jal (cont’d) Control Signal SettingControl Signal Setting RegDstALUOp1 JumpAlUOp0 BranchMemWrite MemReadALUSrc MemtoRegRegWrite MemtoReg1RegDst1