1. Computer organization at the logic level Some not so famous last words

2. Logic diagram of a boolean expression For expression: ((ab + bc’)a)’:

3. Abbreviating diagram Eliminate inverter(s) – show input as x’ instead of x Since a junction just duplicates the signal from a variable, can just show the same variable as many times as needed; we assume any variable or its complement is available as input to any gate

4. Abbreviated version of previous diagram

5. Another example: a’bc  c + a + d)’ Note: diagram assumes (correctly) that XOR has higher precedence than OR and lower than AND

6. Writing a boolean expression from a logic diagram Label the output of each gate with the appropriate subexpression (we assume inputs have labels) Output of the final gate is the full expression

7. Construction Boolean expression from a truth table Can write the non-parenthesized OR of ANDs Each AND is a 1 in the result column of the truth table – see example, next slide

8. Example truth table abcx ------------------------------- 0001 0011 0101 0110 1001 1011 1100 1111 x = 1 for all ANDed combinations except a’bc and abc’ – so one valid expression is: a’b’c’ + a’b’c + a’bc’ + ab’c’ + ab’c + abc

9. Dual technique The previous example illustrates that the OR of ANDs might not produce the simplest expression Alternatively, we can take the AND of ORs; each OR is represented by a 0 in the result column – see next slide

10. Example truth table abcx ------------------------------- 0001 0011 0101 0110 1001 1011 1100 1111 x = 0 for 011 and 110 – so we take the dual, using complements of 0 and 1, with this result: x = (a+b’+c’)(a’+b’+c)

11. Gate delay Gate delay: time it takes for output of a gate to respond to change in its input With long string of gates, delay may be significant Reducing the number of gates reduces gate delay

12. 2-level networks Since any boolean expression can be written as the OR of ANDed terms (2-level and/or network), any function can be implemented with a combinational net with ≤ 2 gate delays The same principle applies to the dual; we can transform the AND of ORed terms, if more convenient, giving us a 2-level or/and network

13. Gate equivalences DeMorgan’s laws tell us that: –(abc)’ = a’+b’+c’ –(a+b+c) = a’b’c’ This leads us to the following equivalences: –an OR gate with inverted inputs is equivalent to a NAND gate –an AND gate with inverted inputs is equivalent to a NOR gate We can replace any AND-OR net with an equivelant NAND-NAND or NAND-NOR net We can make similar replacements for OR-AND nets

14. Equivalent gates

17. Minimizing the number of gates Two-level networks are desirable because of their speed We can sometimes reduce the number of gates in a 2-level network and retain the processing speed of 2 gate delays

18. Example Suppose we start with the 4-input expression a’bd’ + a’c’d’ + a’bc’d’ Recall the absorption properties: –x + xy = x –x(x+y) = x Using commutation and association, we can write the original expression as: a’bd’ + (a’c’d’) + (a’c’d’)b The underlined parts of the expression are recognizable as an ‘x’ term in the first absorption law; thus we can reduce the expression to: a’bc’ + a’c’d’