1. DSP Algorithm on System on Chip Performed by : Einat Tevel Supervisor : Isaschar Walter Accompanying engineers : Emilia Burlak, Golan Inbar Technion - Israel institute of technology department of Electrical Engineering High speed digital systems laboratory winter 2003/2004 With cooperation with RAFAEL

2. Abstract In recent years the world is progressing towards much more sophisticated digital systems, which integrate both hardware and software. In recent years the world is progressing towards much more sophisticated digital systems, which integrate both hardware and software. These devices are known as "System on a Chip" (SoC). These devices are known as "System on a Chip" (SoC). This project explores SoCs, in search of the best implementation of a given DSP algorithm using a SoC. This project explores SoCs, in search of the best implementation of a given DSP algorithm using a SoC.

3. System Description PowerPC 405 Core I-Cache D-Cache CoreConnect Processor Local Bus (PLB) CIC Filters External Memory High Speed Peripherals CoreConnect On-Chip Peripheral Bus (OPB) Low Speed Peripherals PLB-OPB Bridge FPGA Block RAM

4. Data Flow Power PC Data Processing Core Input Data Output Data 12 3 4 1.The data is sent to the Power PC Processor. 2.After parsing the data, The Power PC configures the Data Processing Core and the raw data is sent. 3.The processed data is sent back to the Power PC Processor. 4.The output is ready.

5. Hardware/Software Flow HW Block Diagram HW Description Synthesize P&R BIT File/ Download HW Flow SW Flow Chart Create SW Source Compile Simulate ELF File/ Download SW Flow ISE Design Debug (HW and SW) DATA2BRAM EDK

6. Specification Hardware: Virtex-II Pro FF1152 Development Board Enables implementation of embedded processor based applications using IP cores and customized modules. Includes two integrated PowerPC processors, memory blocks of 8Mx32 SDRAM memory. Virtex-II Pro FF1152 Development Board Enables implementation of embedded processor based applications using IP cores and customized modules. Includes two integrated PowerPC processors, memory blocks of 8Mx32 SDRAM memory. Development and simulation tools: Development and simulation tools: EDK – Embedded Development Kit, CoreGen. EDK – Embedded Development Kit, CoreGen. ISE, ModelSim. ISE, ModelSim.Software: MATLAB, Hyper Terminal. MATLAB, Hyper Terminal.

7. CIC Filters Structure Cascade of Integrators. Cascade of Integrators. Resampling Switch (decimate/expansion). Resampling Switch (decimate/expansion). Cascade of Differentiators. Cascade of Differentiators. Parameters: Number of Stages (N), Rate Change Factor (R), Differential Delay (M). Parameters: Number of Stages (N), Rate Change Factor (R), Differential Delay (M).

8. GUI Screenshot