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Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 9: March 31st Chip Level Simulatio Overall Project Objective: Design an Air-Fuel Ratio Controller for a small gasoline engine with low emissions and low cost Design Manager: Steven Beigelmacher
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Status Design Proposal (done) Architecture (done) High Level C Simulation Behavioral Verilog & Test Bench Floorplan & Structural Verilog Gate Level Design (done) Top Level Schematic Verification Component Layout (done) Analog simulation of SRAM and ROM Layout of all components Component Simulation (done) Smaller Multiplier completed Chip-Level Layout(95%) Top-level LVS errors Still to be done Top level simulation
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12bit Input Reg 8X10 SRAM Value Look-up 12bit Input Reg Engine Speed Manifold Pressure 12bit Input Reg Throttle Position Fixed Point Array Multiplier 2:1Mu x 12bit Output Register Control ROM 12bit Input Reg %Oxygen 7X4 SRAM Comparator Look-up 4:1Mux = R0 12bit Register Win Sin[0:1] 2:1Mu x Rcomp Sin[0:1] Index[0:4] Write R1 R2 RowComp[0]RowComp[1] Srow1 Srow2 RowComp[2] 3bit Reg Wcol Index[0:6] Write Rtable 2:1Mu x Scol ColTable[0:3] 2:1Mu x Scol Valid Wmult1 Wmult2 Smult 5bit State Reg Next[0:4] Wout PulseOut[0:11]
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Design Decisions Redid top-level layout –Divided into three big blocks –Each individual block passes LVS –Top Level should be relatively simple to get working
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Simulation Plan Cannot run full simulation –Requires ~120 cycles to load SRAM and generate first correct outputs Simulate one iteration of comparisons and index generation for lookup table –Only requires ~10 cycles –Verifies any timing and control issues –Multiplier and SRAM lookup table have already been verified –Still simulate whole chip for accurate loading (many transistors will be inactive)
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Mask – Poly & Active
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Mask – Metal 1
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Mask – Metal 2
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Mask – Metal 3
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Mask – Metal 4
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Top Level Layout 383x273(µm)
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Layout 383 x 273 (µm) 104,559 (µm2 ) Aspect Ratio: 1.4 Trans. Density:.167 Tran/ µm 2 Transistor Count = 17,465 Clock Speed 1MHz – speed is not our goal
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Questions????
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