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Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 13 - More about Parasitics; Logical Effort Spring 2007
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ECE 425 Spring 2007Lecture 13 - Logical Effort2 Announcements Reading Book: 4.4-4.5, 4.7-4.8 Weste & Harris Excerpt Verilog Handout (from ECE 313 last year): 1-4, 5.4 Exam 1: Wed. 3/21 Homework due Wed. 3/28: Weste & Harris Problems: 4.3, 4.5, 4.9, 4.10, 4.11, 4.12 Logical Effort References: I. Sutherland, R. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999. N. Weste and D. Harris, CMOS VLSI Design, 3 rd ed, 2004.
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ECE 425 Spring 2007Lecture 13 - Logical Effort3 Where we are Last Time: Combinational Network Delay Today: Effect of Diffusion Parasitics Logical Effort
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ECE 425 Spring 2007Lecture 13 - Logical Effort4 Impact of Diffusion Parasitics on Delay The model ignores parasitics except on output - is this a safe assumption? Consider a 2-input NAND gate - where are the parastics?
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ECE 425 Spring 2007Lecture 13 - Logical Effort5 Parasitics on 2-input NAND How can we estimate C pdiff and C ndiff ?
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ECE 425 Spring 2007Lecture 13 - Logical Effort6 Consider NAND Layout from Lecture 4
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ECE 425 Spring 2007Lecture 13 - Logical Effort7 Consider NAND Layout from Lecture 4
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ECE 425 Spring 2007Lecture 13 - Logical Effort8 Diffusion Parasitics - Summing Up = 0.725fF = 6.465fF
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ECE 425 Spring 2007Lecture 13 - Logical Effort9 Diffusion Parasitics in Large Gates What is the effect of parasitics in a 4-input NAND? Use Elmore Delay
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ECE 425 Spring 2007Lecture 13 - Logical Effort10 Logical Effort - Making Sizing Systematic Invented by Ivan Sutherland, Sun Microsystems Key ideas: Simple linear model of delay - good for hand calculations Account for loading in multiples of min-size inverter capacitance Calculate delays in terms of inverter delay Account for diffusion parasitics on gate outputs Use to predict delay of circuits relative to each other instead of estimating Useful to set sizing from stage to stage Most accurate when no reconvergent fanout
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ECE 425 Spring 2007Lecture 13 - Logical Effort11 Logical Effort - Assumptions Assume that µ p /µ n = 2 (so R p = 2R n ) Assume all basic gates are sized for equal rise/fall time: t r-inv = t f-inv = t r-nand = t f-nand = t r-nor = t f-nor Calculate input loading of each basic gate as a multiple of min-size transistor’s gate capacitance Assume drain diffusion parasitic of a transistor is equal to the transistor’s gate capacitance
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ECE 425 Spring 2007Lecture 13 - Logical Effort12 Transistor Sizing for LE assumptions What are transistor widths as a multiple of min-size? What are the input loads as a multiple of min-size gate cap? Inverter NAND NOR 1 2 2 2 22 4 4 11 Load = 3 Load = 4 Load = 5
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ECE 425 Spring 2007Lecture 13 - Logical Effort13 Logical Effort - Key definitions - delay of a minimum-size inverter driving another inverter (without parasitics) Absolute gate delay: d abs = d * Values of for common processes For 0.6µm process, = 50ps (approx) [Sutherland 99] For a 180nm process, = 15ps (approx) [Weste 04] Gate delay formula: d = f + p Effort delay f is related to gate’s load. Parasitic delay p - due to parasitics in gate itself.
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ECE 425 Spring 2007Lecture 13 - Logical Effort14 Logical Effort - Continued Delay formula (last slide) d = f + p Effort Delay Effort delay has two components: f = g*h Electrical effort h is determined by gate’s load: h = C out /C in Logical effort g is determined by gate’s structure (see next slide) Modified Delay Formula: d = g*h + p
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ECE 425 Spring 2007Lecture 13 - Logical Effort15 Logical Effort (g) of Common Gates Definition: the ratio of input capacitance of the gate to the input capacitance of an inverter that can deliver the same current
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ECE 425 Spring 2007Lecture 13 - Logical Effort16 Logical Effort of Basic Gates Definition: the ratio of input capacitance of the gate to the input capacitance of an inverter that can deliver the same current NOR Inverter NAND 1 2 2 2 22 4 4 11 g = 3/3 = 1 g = 4/3 g = 5/3
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ECE 425 Spring 2007Lecture 13 - Logical Effort17 Parasitic Delay (p) of common gates Assumption for one transistor: diffusion capacitance = gate capacitance Delay due to parasitics on min-size inverter Parastic loading 3C * R = 3*RC = Count diffusion capacitance on output nodes only
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ECE 425 Spring 2007Lecture 13 - Logical Effort18 Logical Effort: Normalized Delay vs. Fanout Inverter 2-Input NAND Electrical Effort: h = C out /C in 1 23456 1 2 3 4 5 6 Parasitic Delay: p Effort Delay: f = gh g = 1 p = 1 d= h + 1 Normallized Delay: d g = 4/3 p = 2 d= (4/3)h + 2 *From Weste & Harris, CMOS VLSI Design d = gh + p
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ECE 425 Spring 2007Lecture 13 - Logical Effort19 Example - Delay Calculations w/ NAND 22 2 2 20 44 4 4 g = 4/3 (from table - p. 14) h = C out /C in = 20/4 = 5 p = 2 (from table - p. 15) d = gh + p = (4/3)*5 + 2 = 8.67 g = 4/3 (unchanged!) h = C out /C in = 20/8 = 2.5 p = 2 (unchanged - why?) d = gh + p = (4/3)*2.5 + 2 = 5.33
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ECE 425 Spring 2007Lecture 13 - Logical Effort20 Example * : FO4 Delay What is the delay of a fanout-of-4 (FO4) inverter? g = 1(from table - p. 14) p = 1(from table - p. 15) h = C out /C in =12/3=4 d = g*h + p = 1*4 + 1 = 5 If =15ps in a 0.18µm technology, d abs = d* = 75ps Note: FO4 delay is often used to characterize the speed of a process d=? *From Weste & Harris, CMOS VLSI Design
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ECE 425 Spring 2007Lecture 13 - Logical Effort21 Example * : Ring Oscillator What is the frequency of an N-stage ring oscillator? g = 1from table - p. 14 p = 1from table - p. 15 h = C out /C in = 1/1 =1 d = g*h + p = 1*2 + 1 = 2 T osc = 2*N*d = 4*Nf osc = 1/T osc = 1/(4*N) Given =15ps in a 0.18µm technology, and N=31 T osc(s) = T osc * = 4*31*15ps = 1.86ns f osc = 1/T osc = 536MHz Ring oscillators often used as process monitors *From Weste & Harris, CMOS VLSI Design N Stages
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ECE 425 Spring 2007Lecture 13 - Logical Effort22 Example * : NOR Driving 10 NORs What is a NOR gate with input capacitance x driving 10 identical NOR gates? g = 9/3from table - p. 14 p = 4from table - p. 15 h = C out /C in = 10x/x = 10 d= g*h + p = 9/3 * 10 + 4 = 34 If =15ps in a 0.18µm technology, d abs = d* = 465ps We don’t need it here, but what is the input loading x? *From Sutherland et. al., Logical Effort
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ECE 425 Spring 2007Lecture 13 - Logical Effort23 Delay in Multiple Stages Path Logical Effort G - LE along a chain of gates: G = g i Path Electrical Effort H - depends on ratio of first and last stage capacitance: H = C out /C in 20 10 x yz g 1 =1 h 1 =x/10 g 2 =5/3 h 1 =y/x g 3 =4/3 h 3 =z/y g 4 =1 h 1 =20/z G = g 1 *g 2 *g 3 *g 4 = 1*5/3*4/3*1 = 20/9H = 20/10 = 2 *From Weste & Harris, CMOS VLSI Design
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ECE 425 Spring 2007Lecture 13 - Logical Effort24 15 5 90 Branching Effort Takes into account fanout Branching effort at one stage: b = (C onpath + C offpath )/ C onpath Branching effort along path: B = b i Path b= (15+15/15) = 2 *From Weste & Harris, CMOS VLSI Design
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ECE 425 Spring 2007Lecture 13 - Logical Effort25 Path Delay Path effort - product of stage efforts F = f i = GBH Path delay - sum of delays of gates along the path: D = g i h i + p i = D F + P D F = f i P = p i
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ECE 425 Spring 2007Lecture 13 - Logical Effort26 Minimizing Path Delay Path effort: F = f i = GBH - independent of sizes Path delay is sum of delays of gates along the path: D = g i h i + p i = D F + P D F = f i P = p i To minimize f i make f i equal in each stage Minimum possible delay in an N-stage path Key Result of Logical Effort. Min delay can be found without calculating the sizes of each gate in path
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ECE 425 Spring 2007Lecture 13 - Logical Effort27 Sizing the Transistors Minimum possible delay in an N-stage path: D=N*F 1/N + P Determine W/L of each gate on path by working backward from the final gate: Capacitance Transformation
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ECE 425 Spring 2007Lecture 13 - Logical Effort28 Example - Transistor Sizing Estimate minimum delay of path from A to B Choose transistor sizes to achieve delay 8 Path x x x y y 45
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ECE 425 Spring 2007Lecture 13 - Logical Effort29 Example - Transistor Sizing Path Logical Effort Branching Effort Path Electrical Effort Path Effort Best Stage Effort Min Delay 8 Path x x x y y 45 H = C out /C in = 45/8 g 1 = 4/3 g 2 = 5/3 g 3 = 5/3 b 1 = 3 p 2 = 3 p 3 = 2 B = b 1 *b 2 *b 1 = 3 * 2 * 1 = 6 G = g 1 *g 2 *g 3 = 4/3 * 4/3 * 5/3 = 100/27 F = G*B*H = 125 45 D = N*F 1/N + P = 3*5 + (2+3+2) = 22 p 1 = 2 b 2 = 2 b 3 = 1
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ECE 425 Spring 2007Lecture 13 - Logical Effort30 Example - Transistor Sizing Now assign transistor sizes using capacitance transformation 8 Path x x x y y 45 g 1 = 4/3 g 2 = 5/3 g 3 = 5/3 p 2 = 3 p 3 = 2 45 p 1 = 2 P 3 = 12 N 3 = 3 P 2 = 4 N 2 = 6 P 2 = 4 N 2 = 4 y = 15 x = 10
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ECE 425 Spring 2007Lecture 13 - Logical Effort31 Example - Transistor Sizing Double-Check: Calculate Delay of Each Stage 8 Path 10 15 45 g 1 = 4/3 g 2 = 5/3 g 3 = 5/3 p 2 = 3 p 3 = 2 45 p 1 = 2 h 1 = (10+10+10)/8 = 3.75 h 2 = 2 h 3 = 2 d i = g i *h i + p i d 1 = (4/3)*3.75 + 2 = 7 h 2 = (15+15)/10 = 3 d 2 = (5/3)*3 + 3 = 8 h 3 = 45/15 = 3 d 3 = (5/3)*3 + 2 = 7 D = d 1 + d 2 + d 3 = 22
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ECE 425 Spring 2007Lecture 13 - Logical Effort32 Choosing the Best Number of Stages Which buffer circuit is fastest? NfD 1 2 3 4 64 8 4 2.8 65 18 15 15.3 8x 4x16x 2.8x 8x23x
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ECE 425 Spring 2007Lecture 13 - Logical Effort33 Choosing the Best Number of Stages The General Case - What should N be?
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ECE 425 Spring 2007Lecture 13 - Logical Effort34 Example: Decoder Design Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. Decoder Register File 16 A[3:0] A’[3:0] 32 bits 16 words
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ECE 425 Spring 2007Lecture 13 - Logical Effort35 Example: Decoder Design Decoder specifications: 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors Ben needs to decide: How many stages to use? How large should each gate be? How fast can decoder operate? DecoderRegister File 16 A[3:0] A’[3:0] 32 bits 16 words
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ECE 425 Spring 2007Lecture 13 - Logical Effort36 One Possible Design - 3 Stages Decoder effort is mostly electrical and branching If we neglect logical effort (assume G = 1) Try a 3-Stage Design Electrical Effort:H = (32*3)/10 = 9.6 Branching Effort:B = 8 Path Effort: F = GBH = 76.8 Number of StagesN = log 4 F = 3.1
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ECE 425 Spring 2007Lecture 13 - Logical Effort37 3-Stage Decoder Design b 1 =8 b 2 =1b 3 =8 g 2 =6/3
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ECE 425 Spring 2007Lecture 13 - Logical Effort38 Gate Sizes - 3-Stage Decoder Electrical Effort:H = (32*3)/10 = 9.6 Branching Effort:B = 8 Path Logical Effort:G = (1*6/3*1) = 2 Path Effort:F = GBH = 2*9.6*8 = 153.6 Stage Effort:
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ECE 425 Spring 2007Lecture 13 - Logical Effort39 Decoder - Alternative Designs 21.6816/96NAND2-INV-NAND2-INV-INV-INV 20.4716/95INV-NAND2-INV-NAND2-INV 19.7616/94NAND2-INV-NAND2-INV 20.5620/94NAND2-NOR2-INV-INV 21.1724NAND4-INV-INV-INV 22.1623INV-NAND4-INV 30.1420/92NAND2-NOR2 29.8522NAND4-INV DPGNDesign
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ECE 425 Spring 2007Lecture 13 - Logical Effort40 Summary of Notation D = d i = D F + P d = f + pdelay P = p i p (see table)parasitic delay D F = f i feffort delay F = GBHf = gheffort B = b i branching effort electrical effort G = g i g (see table)logical effort N1number of stages PathStageTerm
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ECE 425 Spring 2007Lecture 13 - Logical Effort41 Summary - The Method of Logical Effort Compute the path effortF = GBH Estimate the best number of stages Sketch a path using: Estimate the minimum delay: D=N*F 1/N + P Determine the best stage effort: Starting with output, work backward to find sizes:
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ECE 425 Spring 2007Lecture 13 - Logical Effort42 Limitations of Logical Effort Chicken and egg problem Need path to compute G But don’t know number of stages without G Simplistic delay model Neglects input rise time effects Neglects parasitics not on output node Interconnect Iteration required in designs with wire Maximum speed only Not minimum area/power for constrained delay
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ECE 425 Spring 2007Lecture 13 - Logical Effort43 Summary Logical effort is useful for thinking of delay in circuits Numeric logical effort characterizes gates NANDs are faster than NORs in CMOS Paths are fastest when effort delays are ~4 Path delay is weakly sensitive to stages, sizes But using fewer stages doesn’t mean faster paths Delay of path is about log 4 F FO4 inverter delays Inverters and NAND2 best for driving large caps Provides language for discussing fast circuits But requires practice to master
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ECE 425 Spring 2007Lecture 13 - Logical Effort44 Coming Up Testing Comb. Logic Design using Standard Cells Sequential Logic
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