1. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 5 Arithmetic and Logic Instructions Barry B. Brey bbrey@ee.net

2. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Addition The ADD instruction is used for binary addition. The ADD instruction is used for binary addition. The addition causes the flag bits to change. The addition causes the flag bits to change. Addition can be 8-, 16-, and 32-bits. Addition can be 8-, 16-, and 32-bits. All of the addressing modes presented in Chapter 2 are used by addition. All of the addressing modes presented in Chapter 2 are used by addition. ADD EAX,EBX ;EAX = EAX + EBX

3. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Increment The INC instruction adds a one to a register or the contents of a memory location. The INC instruction adds a one to a register or the contents of a memory location. INC BX;BX = BX + 1 INC BYTE PTR [EBX]

4. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Add with Carry The ADC instruction adds the carry bit into the sum. Used for wide additions (wider than 32-bits) and other reasons. The ADC instruction adds the carry bit into the sum. Used for wide additions (wider than 32-bits) and other reasons. ADC AX,DX;AX = AX + DX + C ADX ESI,[EBX]

5. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

6. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Subtraction The SUB instruction performs subtraction and the flags change to reflect condition of the result. The SUB instruction performs subtraction and the flags change to reflect condition of the result. As with other arithmetic and logic instructions, subtraction exists for 8-, 16-, and 32-bit data. As with other arithmetic and logic instructions, subtraction exists for 8-, 16-, and 32-bit data. SUB AL,3;AL = AL - 3 SUB ECX,ESI

7. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Decrement The DEC instruction subtracts one from a register or the contents of a memory location. The DEC instruction subtracts one from a register or the contents of a memory location. DEC EBX;EBX = EBX - 1 DEC DWORD PTR [EAX]

8. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Subtract with Borrow The SBB instruction subtracts with borrow (where the borrow is held in the carry flag). The SBB instruction subtracts with borrow (where the borrow is held in the carry flag). SBB EAX,EBX ;EAX = EAX – EBX – C

9. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

10. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Compare The CMP instruction is a special form of the SUB instruction. A compare does not result in a difference that is saved, on the flag bits change to reflect the difference. The CMP instruction is a special form of the SUB instruction. A compare does not result in a difference that is saved, on the flag bits change to reflect the difference. CMP AL,3 ;if AL = 3 the result to zero (flag)

11. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Multiplication The MUL (unsigned) and IMUL (signed) instruction exist to perform 8-, 16-, or 32- bit multiplication. The MUL (unsigned) and IMUL (signed) instruction exist to perform 8-, 16-, or 32- bit multiplication. The result is always a double wide result. The result is always a double wide result. The carry and overflow bits indicate conditions about the multiplication. The carry and overflow bits indicate conditions about the multiplication. A special IMUL exists with 3 operands. A special IMUL exists with 3 operands.

12. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Division The DIV (unsigned) and IDIV (signed) instruction exist to perform division on 8-, 16-, or 32-bit numbers. The DIV (unsigned) and IDIV (signed) instruction exist to perform division on 8-, 16-, or 32-bit numbers. Division is always performed o a double wide dividend. Division is always performed o a double wide dividend. The result is always in the form of an integer quotient and an integer remainder. The result is always in the form of an integer quotient and an integer remainder.

13. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e AND The AND instruction performs logical multiplication (the AND operation). The AND instruction performs logical multiplication (the AND operation).

14. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e OR The OR instruction generates the logical sum (OR operation). The OR instruction generates the logical sum (OR operation).

15. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Exclusive OR The XOR instruction performs the Exclusive OR operation. The XOR instruction performs the Exclusive OR operation.

16. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e NEG and NOT The NEG (negate) instruction 2’s complements a number, The NEG (negate) instruction 2’s complements a number, The NOT instruction 1’s complements a number. The NOT instruction 1’s complements a number. NOT EAX NEG DWORD PTR [EBX]

17. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Shifts There are 4 shift instructions. Two are logical shifts and two are arithmetic shifts. There are 4 shift instructions. Two are logical shifts and two are arithmetic shifts. The logical shifts reposition the bits in a number. The arithmetic shifts multiply or divide signed numbers by powers of two. The logical shifts reposition the bits in a number. The arithmetic shifts multiply or divide signed numbers by powers of two. SHR and SHL are logical and SAR and SAL are arithmetic shifts. SHR and SHL are logical and SAR and SAL are arithmetic shifts. SHL AL,3 or SHL AL,CL

18. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

19. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Rotates Rotates are shifts that re-circulate the bit that moves out of an end of the register or memory location. Rotates are shifts that re-circulate the bit that moves out of an end of the register or memory location. Four rotates exist where two just rotate the target and two rotate the target through the carry flag. Four rotates exist where two just rotate the target and two rotate the target through the carry flag. ROL AL,3or RCL AL,3

20. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

21. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e TEST The TEST instruction is a special form of the AND instruction that produces no result except for a change of the flags. The TEST instruction is a special form of the AND instruction that produces no result except for a change of the flags. This instruction is often used to test multiple bits of a number. This instruction is often used to test multiple bits of a number. TEST AL,3 ;test the right two bits (if both are zero the result is zero)

22. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Bit Test Instructions There are four bit test instructions BT (bit test), BTR (bit test and reset), BTS (bit test and set), and BTC (bit test and complement). There are four bit test instructions BT (bit test), BTR (bit test and reset), BTS (bit test and set), and BTC (bit test and complement). Each tests the prescribed bit by moving it into carry. Then the bit is modified (except for BT) Each tests the prescribed bit by moving it into carry. Then the bit is modified (except for BT) BT AL,3;bit 3 is moved to carry BTS AL,3;bit 3 is moved to carry then set BTS AL,3;bit 3 is moved to carry then set BTR AL,3;bit 3 is moved to carry then reset BTC AL,3;bit 3 is moved to carry then inverted.

23. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e String Compares The SCAS and CMPS instruction perform comparisons on blocks of data. The SCAS and CMPS instruction perform comparisons on blocks of data. SCAS compares a memory block to the accumulator and CMPS compares two blocks of memory. SCAS compares a memory block to the accumulator and CMPS compares two blocks of memory. SCASB, SCASW, and SCASD are available for 8-, 16-, and 32-bit comparisons as are CMPSB, CMPSW, and CMPSD. SCASB, SCASW, and SCASD are available for 8-, 16-, and 32-bit comparisons as are CMPSB, CMPSW, and CMPSD.

24. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e SCAS is often used to search for a value and CMPS is often used to compare two blocks. SCAS is often used to search for a value and CMPS is often used to compare two blocks. Both instruction change the flags to indicate the outcome of the comparison. Both instruction change the flags to indicate the outcome of the comparison. The Direction flag determines whether the pointer increments or decrements. The Direction flag determines whether the pointer increments or decrements. REPE and REPNE are often used to repeat the SCAS or CMPS instructions. REPE and REPNE are often used to repeat the SCAS or CMPS instructions.

25. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e AAM About the only ASCII adjust instruction commonly used is the AAM instruction. About the only ASCII adjust instruction commonly used is the AAM instruction. This instruction divides by 10, but leaves the quotient in AH instead of AL. The remainder is found in AL instead of AH. This instruction divides by 10, but leaves the quotient in AH instead of AL. The remainder is found in AL instead of AH. By dividing by 10, a number up to 100 decimal can be converted to BCD. By dividing by 10, a number up to 100 decimal can be converted to BCD.

26. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e DAA and DAS These instructions are used to adjust the result after a BCD addition or subtraction. These instructions are used to adjust the result after a BCD addition or subtraction. DAS and DAA does find some application in systems. DAS and DAA does find some application in systems.