1. Primary Contributions  Derive inversion based VPEC (Vector Potential Equivalent Circuit) model from first principles.  Replace inductances with effective resistances  Enable direct and more efficient simulation in SPICE  Prove that circuit matrix in VPEC model is strictly diagonal dominant and hence passive.  Enable various passivity-preserved sparsifications and achieve 1000x simulation speedup and storage reduction  de facto model PEEC  Accurate model needs detailed discretization of conductors  Volume filaments for non-uniform current distribution  Surface panels for non-uniform surface charge distribution  Segments for quasi-static approximation  Distributed RLC circuit has coupling inductance between any two segments  Total 3,278,080 elements for 128b bus with 20 segments per line  162M storage for SPICE netlist small surface panels with constant charge thin volume filaments with constant current Differential Maxwell EquationsVector Potential for filaments  Inductance can be modeled by effective resistances  Resulting circuit below can be analyzed by SPICE  Runtime of full PEEC grows exponentially, but sparsified VPEC grows lineally  Full VPEC has the same accuracy as full PEEC but faster (47x for 256-bit bus)  Sparsified VPEC reduces runtime and storage by 1000x with bounded error for large scale interconnects  Truncate small-valued off-diagonal elements in circuit matrix  Runtime includes LU inversion  Full VPEC model is faster but yet exact compared to full PEEC model  Increased truncation threshold leads to reduced runtime and slightly lower accuracy Models Truncating Thresholds No. of Elements Run-time (s)Average Volt. Diff. (V) Standard Dev. (V) Full PEEC8256281.0200 Full VPEC825636.40-1.64e-63.41e-4 Truncated VPEC (5e-5)748230.894.64e-64.97e-4 Truncated VPEC (1e-4)539219.551.29e-51.37e-3 Truncated VPEC (5e-4)25178.353.77e-45.20e-3 Numerical sparsification for 128-bit bus with 1 segment per line VPEC Circuit Equation Extraction of Effective Resistances Main Theorem The circuit matrix is strictly diagonal dominant and positive-definite Corollary The VPEC model is still passive after truncating off-diagonal elements  Calculate PEEC elements via either formula or FastHenry/FastCap  Invert L matrix with  LU/Cholesky factorization  GCR/GMRES Iteration  Generate full VPEC that replaces inductance by effective resistance, current and voltage sources  Sparsify full VPEC using numerical or geometrical truncations  Simulate sparsified VPEC via SPICE Windowed VPEC 32-bit bus with 8 segments per line  Forwarded coupling is negligible  Sparsified VPEC has high accuracy for windows as small as (8,2) IEEE/ACM Design Automation Conference 2003 Section 43 Partially Sponsored by NSF and Analog Devices VPEC: Provably Passive and Cost Efficient RLC Modeling Student: Hao Yu Advisor: Lei He Electrical Engineering Dept, UCLA, http://eda.ee.ucla.edu Models and Settings No. of Elements Run Time (s) Avg. Volt. Diff. (V) Standard Dev. (V) Full PEEC328962535.4800 Full VPEC (32, 8) 32896772.891.00e-5 6.26e-4 Windowed (32, 2) 11392 311.22 5.97e-5 1.84e-3 Windowed (16, 2) 3488 152.57-1.23e-4 4.56e-3 Windowed (8, 2) 2240 85.14 -2.17e-4 8.91e-3 Interconnect Model Challenge of Inductive Modeling VPEC Model Inversion Based VPEC VPEC Based Interconnect Modeling Runtime Scaling Geometrical Sparsification Numerical Sparsification  Inductance matrix is dense and not diagonal dominant  Truncating off-diagonal elements results loss of passivity  Existing passivity-guaranteed sparsification methods lack accuracy or theoretical justification  Returned-loop [Shepard:TCAD¡’00]  Shift-truncation (shell) [Krauter:ICCAD’95, Pilleggi:TCAD’01]  K-element [Devgan:ICCAD’00, Ji: DAC’01]  Localized VPEC [Pacelli:ICCAD¡’02]