1. 1 Random Number Generator Dmitriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan April 12, 2006 Top-Level Layout Project Objective: Create a Cryptologically Secure Pseudo-Random Number Generator that will revolutionize chaos

2. 2 Status C implementation Architecture Behavioral Design and Simulation Gate-Level Design and Simulation Preliminary Floorplan Schematic Design and Simulation Revised Floorplan  Layout SRAM Adder Registers Counters Control Logic Modules Datapath  Global Layout (~75% complete)  Simulations Adder SRAM Registers  Register to Register Analysis  Layout Optimizations

3. 3 Design Decisions Global Layout Assembly Order –Complete upper and lower sections separately –Merge the sections into the datapath –Add control logic to global layout one piece at a time

4. 4 Global Layout: Upper

5. 5 Global Layout: Lower

6. 6 Global Layout: Datapath

7. 7 PartTrans Count AreaDensityProp Delay Schematic #s ExtractRC #s Power (1x) @ 500MHz Adders (4) 5,856 (1,464 ea.) 25,200 um2 (6,300um2 ea.) 0.2321.45 ns 1.56 ns 600 uW 620 uW SRAM (M&R) 17,736 (M=10,458 R=7,278) 51,000 um2 (M=35,000 R=16,000 0.348 (M=0.293 R=0.456) 735ps 845ps W: 510 uW W: 3.25 mW R: 190 uW R: 1.40 mW Registers (10) 6400 (640 ea.) 38,400um2 (3,840um2 ea.) 0.167220 ps 275 ps 530 uW 590 uW Total33225182,000um20.1832ns (500 MHz Clk) Putting it All Together

8. 8 Too Many Hands… Bottleneck I –During Verilog Design, one or two people worked on the code at a time Parallelized –During the bulk of layout, everyone could be working on different modules at the same time. We had five layouts going at once. Bottleneck II –Control logic can only be laid out by one or two people at a time

9. 9 Questions? Comments?