1. Constructing Current-Based Gate Models Based on Existing Timing Library Andrew Kahng, Bao Liu, Xu Xu UC San Diego http://vlsicad.ucsd.edu

2. Outline Gate Modeling Background Problem Formulation Approximation and Regression Applications Experiments Conclusion

3. Gate Models K-factor lookup tables 1. Dg = f(Cload, Tr) 2. Tr out = g(Cload, Tr) Efficient capacitance Ceff for distributed load capacitance  To achieve identical gate delay (and output signal transition time at the same time!)  E.g., by achieving the same average gate output current

4. Calculating Effective Capacitance 1.If (Ceff > Cload || Ceff < 0) 2. Return Cload 3.Else if(  Ceff <  ) 4. Return Ceff 5.Else 6. Continue iteration May not converge No equivalent gate delay and Trout at the same time Waveforms are not ramp functions! Tr out = g(Ceff, Tr) Ceff s.t. Iout(Ceff)=Iout(load) Ceff = Cload

5. Current-Based Transistor Model MOSFET is a voltage-controlled current source, e.g., as in the alpha-power-law model For a simple inverter, gate output current is given by one of the transistors An equivalent inverter macro-model for an inverting complex gate  current-based gate modeling

6. Current-Based Gate Modeling Consists of a lookup table I(Vi, Vo) and C(Vi, Vo) Transient analysis for output signal waveform ViI(Vi, Vo) C RVoVi Voltage-Based Current-Based

7. Gate Pre-Characterization Current-based gate models need additional pre- characterization, e.g., I(Vi, Vo), given by SPICE DC sweep analysis Cadence Effective Current Source Model (ECSM) Synopsys Composite Current Source Model (CCS) Rise_transition (template) { index_1: // slew rate index_2: // load cap values: // output Tr ecsm_waveform (name1) { index_3: // output voltage values: // time point }

8. Outline Gate Modeling Background Problem Formulation Approximation and Regression Applications Experiments Conclusion

9. Constructing Current-Based Gate Model From Existing Timing Libraries Given gate delays and output slew rates for load caps and input slew rates, find an equivalent current-based gate model, e.g., I(Vi, Vo) and C ViI(Vi, Vo) C 1. Dg = f(Cload, Tr) 2. Tr out = g(Cload, Tr) Tr Cload Dg Tr Cload Tr out Vo Vi I C

10. To find an unknown underlying physical process by a set of measurements Q = C V Inhomogeneous Fredholm integral equations of the first kind Inverse Problem

11. Integral equations  differential equations Apply interpolation to reduce variables to those in the I(Vi, Vo) lookup table Inverse problem solutions are extremely sensitive to input data perturbations! Inverse problem  Optimization w/ objective A +  S (A: accuracy, S: smoothness,  : weighting factor) Solving an Inverse Problem

12. Outline Gate Modeling Background Problem Formulation Solution: Approximation and Regression Applications Experiments Conclusion

13. Polynomial Regression of I(Vi,Vo) A priori knowledge: Approximate I(Vi, Vo) by a quadratic polynomial 9+1 coefficients in a limited range

14. Polynomial Regression of I(Vi,Vo)

15. 1.Start with an initial polynomial coefficient 2.For each iteration 3. Perturb a coefficient a i ’ = a i +  4. Compute mean square gate delay mismatch  5. If  reduces, commit perturbation a i = a i +  6. Else, go other direction a i = a i –  7. Stop if no improvement 8. Reduce step  for another iteration 9.Compute I(Vi, Vo) and C Our Constructive Method

16. Applications More accuracy, arbitrary waveform Efficiency advantage over SPICE simulation Gate delay calculation for  Long interconnects  Cross-coupling interconnects  Supply voltage drop effect Supply current calculation Noise calculation

17. Supply Voltage Variation Effect on Gate Delay Calculation There exists an equivalent inverter macro-model for each input combination for any (inverting) complex gate Adjust input and output voltages for I(Vi, Vo) table lookup for a falling input signal, but not for a rising input signal

18. Experiments BPTM 70nm technology cell library Compare (our) constructed and (SPICE simulation based) pre-characterization models Our Constructed Quad. Pre - Characterization Cubic Pre - Characterization  invx41.255.79.7345.211.1237.8 invx81.8516.912.9327.214.6727.8 nor2x40.464.87.06152.75.9156.5

19. Experiments Gate delays by (1) our model and (2) pre-characterized model normalized by SPICE simulation results For Ideal (1.0V) Supply Voltage (1)93.097.499.0101.097.894.995.798.0 (2)100.098.799.3100.0102.5101.2100.6100.0 (1)98.4102.699.095.5103.9100.8100.299.5 (2)104.3101.8100.0 97.698.599.2100.1 For Degraded (0.9V) Supply Voltage (1)102.0105.4106.7108.6101.2106.8108.6106.9 (2)102.199.898.798.8100.899.698.797.9 (1)107.8106.4106.6106.2107.8106.4106.6108.3 (2)100.099.699.197.895.697.998.7100.2

20. Summary Utilize existing timing libraries for application of novel current-based gate modeling Wide range of applications: supply current calculation, delay calculation for complex waveforms, e.g., resistive shielding, crosstalk coupling, supply voltage variation, etc. Slightly less accurate than pre-characterized current-based gate models, e.g., within 8.6% vs. 4.4% for gate delay calculation with varied supply voltage Reasonable runtime for model construction, 28.3 seconds in average on a 2.8GHz P4 system

21. Thank you !