1. Viterbi Decoder: Presentation #2 Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun M1 Overall Project Objective: Design of a high speed Viterbi Decoder Stage 2: 26 Jan. 2004 Architecture Proposal Design Manager: Yaping Zhan

2. Status Design Proposal (finalized) Architecture Proposal (done) Final Algorithm Description Mapping of Algorithm into hardware High level simulation/emulation in Matlab Behavioral Verilog simulation and test bench To be done: Floor Plan Gate Level Design Component Layout Chip Layout Spice Simulation of Entire Chip 18-525, Integrated Circuits Design Project

3. Viterbi Algorithm Description Branch Calculation Unit Add Compare Select Unit Maximum Likelihood Path Search Trace FIFOTrace Back Control Unit Overview of Algorithm 18-525, Integrated Circuits Design Project Aim: Retrieve data from the disk Algorithm based upon maximum likelihood detection 01000111, 01001111 Viterbi Decoder 01100101, 00001111 BADGOOD

4. Viterbi Algorithm Description Pseudo-Code Step 1: Send it to the Branch and Compare Unit (BCU) Subtract it with 16 constants C = [0 -1 -1 -2 1 0 0 -1 1 0 0 -1 2 1 1 0] Square each result Step 2: Send the results to Add Compare Select Unit (ACU) Select minimum of 2 results, add using feedback loop and send to ML Store position of minimum selected and send to trace back Step 3: Maximum Likelihood Path Search (ML) Find minimum value of all inputs Find and store position Step 4: Trace Back Go back along the path to find the correct input sequence For each digit in the input sequence do: 18-525, Integrated Circuits Design Project

5. D D … … D D D D DD D D … … ……….. … C0C1C2C3Cn-1Cn ……….. Control Logic Input Output BCU ACS ML Search FIFO & trace back Input_valid Clock Vdd Gnd Output_valid Reset Viterbi Algorithm Description Flow-chart

6. Branch and Compare Unit (BCU) Add Compare Select Unit (ACS) 18-525, Integrated Circuits Design Project C0C1C2C3 BCU C0C1C2C3 C0C1C2C3 C0C1C2C3 Input ACS

7. Maximum Likelihood Path Search (ML) 18-525, Integrated Circuits Design Project ML Search

8. Trace Back Unit 18-525, Integrated Circuits Design Project DD D D DD D D DD D D DD D D DD D D DD D D ………………………………………………….

9. 18-525, Integrated Circuits Design Project Matlab Simulation

10. 18-525, Integrated Circuits Design Project Matlab Simulation (Test Results)

11. 18-525, Integrated Circuits Design Project Verilog Simulation

12. 18-525, Integrated Circuits Design Project Verilog Simulation (Test Result) Match with Matlab Result

13. Questions? 18-525, Integrated Circuits Design Project