1. The Development of Psec-Resolution TDC for Large Area TOF Systems Fukun Tang Enrico Fermi Institute University of Chicago With Karen Byrum and Gary Drake (ANL) Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David Yu (UC)

2. Major advances for TOF measurements: Ability to simulate electronics and systems to predict design performance Output at anode from simulation of 10 particles going through fused quartz window- T. Credo, R. Schroll Jitter on leading edge 0.86 psec From H. Frisch

3. Requirement: Psec-Resolution TDC 1 ps Resolution Time-to-Digital Converter!!! Start Stop 500pS Tw MCP_PMT Output Signal Reference Clock

4. Diagram of MCP-PMT Electronics From Harold

5. (1) TAC-ADC Approaches & Possibilities Receiver “Zero”-walk Disc. TAC Driver11-bit ADC 2 Ghz PLL 4x1Ghz PLL REF_CLK PMT psFront-end (Timing Module Option #1) 1/4

6. TAC-ADC: Simulation Result Electronics with typical gate jitters << 1 psec

7. (2) Time Stretcher Approaches & Possibilities Receiver “Zero”-walk Disc. Stretcher Driver11-bit Counter 2 Ghz PLL REF_CLK PMT psFront-end (Timing Module Option #2) 1/4 CK5Ghz

8. Time Stretcher: Simulation Result 1ns Time Interval (Input Signal) Stretched Time = 274ns (pedestal=74ns) x200 Stretched Time Interval (Output Signal ) 0 50ns 100ns 150ns 200ns 250ns 300ns

9. Ultimate Goal: To build TDC with 1 pSec Resolution for Large Scale of Time-of-Flight Detector. To build TDC with 1 pSec Resolution for Large Scale of Time-of-Flight Detector. Primary Goal: To build 2-Ghz VCO, key module of PLL that generates the TDC reference signal To build 2-Ghz VCO, key module of PLL that generates the TDC reference signal Cycle-to-Cycle Time-jitter < 1 ps Cycle-to-Cycle Time-jitter < 1 ps To evaluate IHP SG25H1/M4M5 Technology for our applications To evaluate IHP SG25H1/M4M5 Technology for our applications To gain experiences on using Cadence tools (Virtuoso Analog Environment) To gain experiences on using Cadence tools (Virtuoso Analog Environment) Circuit Design (VSE) Circuit Design (VSE) Simulation (Spectre) Simulation (Spectre) Chip Layout (VLE, XLE, VCAR) Chip Layout (VLE, XLE, VCAR) DRC and LVS Check (Diva, Assura, Calibre) DRC and LVS Check (Diva, Assura, Calibre) Parasitic Extraction (Diva) Parasitic Extraction (Diva) Post Layout Simulation (Spectre) Post Layout Simulation (Spectre) GDSII Stream out GDSII Stream out Validation Validation Tape Out Tape Out VCO: Submission of Oct. 2006

10. 1N1N Diagram of Phase-Locked Loop PD CP I1I1 I2I2 LF VCO F ref F0F0 Uc PD: Phase Detector CP: Charge Pump LF: Loop Filter VCO: Voltage Controlled Oscillator

11. IHP (SG25H1) 0.25  m SiGe BiCMOS Technology 0.25  m BiCMOS technology 0.25  m BiCMOS technology 200Ghz NPN HBT (hetero-junction bipolar transistor) 200Ghz NPN HBT (hetero-junction bipolar transistor) MIM Capacitors (layer2-layer3) ( 1f/1u 2 ) MIM Capacitors (layer2-layer3) ( 1f/1u 2 ) Inductors (layer3-layer4) Inductors (layer3-layer4) High dielectric stack for RF passive component High dielectric stack for RF passive component 5 metal layers (Al) 5 metal layers (Al) Digital Library: Developing Digital Library: Developing

12. SG25 Process Specification

13. 2-GHz BiCMOS VCO Schematic Negative Resistance and Current-Limited Voltage Control Oscillator with Accumulating PMOS Varicap and 50  Line Drivers

14. V-F Plot (3 model cases @ 27C-55C) Temperature: 27C-55C Supply: VDD=2.5V VControl varied 0.18V VControl Frequency

15. Best -89.94 dBc/Hz Typical -89.58 dBc/Hz Worst -89.90 dBc/Hz Phase Noise ( 3 model cases @ 27C) Worst Typical Best @100KHz offset Temperature: 27C Supply: VDD=2.5V

16. Calculation of Cycle-to-Cycle Jitter

17. 2-GHz VCO Performance Summary (1) T=27C f 0 = 2 GHz phase noise: dBc/Hz@100K offset Vcontrol(V)Itail(mA)Vpp(mV)Icc(mA)Pw(mW) Phase Noise Best1.5410.9063533.9285.0-89.75 Typical1.608.8357327.6367.5-89.54 Worst1.687.4852422.3156.0-89.18

18. 2-GHz VCO Performance Summary (2) T=55C f 0 = 2 GHz phase noise: dBc/Hz@100K offset Vcontrol(V)Itail(mA)Vpp(mV)Icc(mA)Pw(mW) Phase Noise Best1.5610.5062834.4886.3-89.15 Typical1.648.6357128.0570.0-88.72 Worst1.707.3852122.5756.5-88.56

19. Virtuoso XL Layout View

20. Virtuoso Chip Assembly Router View

21. Diagram of Post Layout Simulation Schematic Analog_extracted

22. Transit Analysis: Comparison of Schematic and Post Layout Simulations Schematic Post Layout Outputs@50  loads

23. V-F Plot: Comparison of Schematic and Post Layout Simulations Post Layout Schematic Vcontrol Frequency

24. Phase Noise: Post Layout Simulations VDD=2.5V Temp.=27C, 55C Phase Noise @100KHZ offset27C -89.40 dBc/Hz (Sch: -89.75) 55C -88.90 dBc/Hz (Sch: -89.15)

25. Conclusion (1) VCO time-jitter met our requirement. (2) Post layout simulation matched schematic simulation very well. (3) Some problems we have encountered with pcell library, layout, DRC, LVS and auto-routing functionalities. (4) Ready for October Submission.