Presentation is loading. Please wait.

Presentation is loading. Please wait.

Instituto de Plasmas e Fusão Nuclear Instituto Superior Técnico Lisbon, Portugal B.B. Carvalho | Lisbon, February 16, 2009 |

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "Instituto de Plasmas e Fusão Nuclear Instituto Superior Técnico Lisbon, Portugal B.B. Carvalho | Lisbon, February 16, 2009 |"— Presentation transcript:

1 Instituto de Plasmas e Fusão Nuclear Instituto Superior Técnico Lisbon, Portugal http://www.ipfn.ist.utl.pt B.B. Carvalho | Lisbon, February 16, 2009 | Diagnostics & Data Acquisition High Performance Logic Devices 2 nd Advanced Course on Diagnostics and Data Acquisition Bernardo Brotas Carvalho bernardo@ipfn.ist.utl.pt

2 Author’s name | Place, Month xx, 2007 | Event 2 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Programmable logic devices Some history Digital Logic Circuits (state machines, controllers, counters, registers, and decoders, etc..) Lots of SSI (small-scale integration) chips (7400-series parts)

3 Author’s name | Place, Month xx, 2007 | Event 3 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition PROM as Combinatorial Circuits 10111000 Address Lines (input) 0011011010111001 Data Lines (outputs) a0a0 a1a1 a2a2 b0b0 b1b1 b2b2 Example: (a 2, a 1, a 0 ) = (010) ->b 0 = 1 Have to decode ALL the input combinations. Very inefficient

4 Author’s name | Place, Month xx, 2007 | Event 4 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Programmable Array Logic (PAL) a0a0 a1a1 b0b0 Example: b 0 =F(a 1, a 0 ) = a 1. a 0 + a 1. a 0 X X X X Fixed-OR, programmable-AND Plane PLA had TWO two levels of programmable logic an AND plane and an OR plane (more expense to manufacturing and poor speed performance) Are the basis of some of the newer, more sophisticated architectures

5 Author’s name | Place, Month xx, 2007 | Event 5 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition PAL Configurations PAL16L8 = 8 combinational outputs PAL16R8 = 8 registered outputs PAL16V8 = 8 “variable” outputs PAL 16R4 Block Diagram

6 Author’s name | Place, Month xx, 2007 | Event 6 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition PAL Programming Languages PALASM TITLE video ; shift register CHIP video PAL20V8 CK /LD D0 D1 D2 D3 D4 D5 D6 D7 CURS GND NC REV Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 /RST VCC ( PAL pins in numerical order starting with pin 1 ) STRING Load 'LD*/REV*/CURS*RST' ; load data (Comment ) STRING LoadInv 'LD*REV*/CURS*RST' ; load inverted of data STRING Shift '/LD*/CURS*/RST' ; shift data from MSB to LSB EQUATIONS /Q0 := /D0*Load+D0*LoadInv:+:/Q1*Shift+RST ( Registered assignment ) Q6 = D1 + /D2 ( Combinatorial assignment )

7 Author’s name | Place, Month xx, 2007 | Event 7 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition ABEL (Advanced Boolean Expression Language) module MUX4 title '4:1 MUX' MyDevice device 'P16L8' ; @ALTERNATE "inputs A, B, /P1G1, /P1G2 pin 17,18,1,6 "LS153 pins 14,2,1,15 P1C0, P1C1, P1C2, P1C3 pin 2,3,4,5 "LS153 pins 6,5,4,3 P2C0, P2C1, P2C2, P2C3 pin 7,8,9,11 "LS153 pins 10,11,12,13 "outputs P1Y, P2Y pin 19, 12 "LS153 pins 7,9 equations P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3); end MUX4 PAL Programming Languages

8 Author’s name | Place, Month xx, 2007 | Event 8 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition SPLD Programming Cycle

9 Author’s name | Place, Month xx, 2007 | Event 9 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Programming PALs PROM ( blow fuses permanently) E-PROM (UV erasable PROM) Specialized/universal device programmer

10 Author’s name | Place, Month xx, 2007 | Event 10 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Complex Programmable Logic Devices (CPLDs) Internal structure of a CPLD PAL (eg 22V10) I/O CPLDs provide logic capacity up to the equivalent of about 50 typical SPLD devices I/O Typical I/O Block

11 Author’s name | Place, Month xx, 2007 | Event 11 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition FPGA Architecture A bunch of simple, configurable logic blocks arranged in an array with interspersed switches that can rearrange the interconnections between the logic blocks Logic Block Switch Matrix Interconnection Resources Additionally, clock circuitry for driving the clock signals to each logic block, and additional logic resources such as ALUs, memory, and Decoders or full microprocessors

12 Author’s name | Place, Month xx, 2007 | Event 12 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Simplified view of a FPGA Logic Cell

13 Author’s name | Place, Month xx, 2007 | Event 13 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition LUT (Look-Up Table) Functionality Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs

14 Author’s name | Place, Month xx, 2007 | Event 14 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Basic I/O Block Structure D EC Q SR D EC Q SR D EC Q SR Three-State Control Output Path Input Path Three-State Output Clock Set/Reset Direct Input Registered Input FF Enable

15 Author’s name | Place, Month xx, 2007 | Event 15 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered –advised for high-performance I/O Inputs can be delayed

16 Author’s name | Place, Month xx, 2007 | Event 16 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition PLD Programming Technologies EPROM “AND” GATE FPGA SRAM Anti-Fuse

17 Author’s name | Place, Month xx, 2007 | Event 17 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Logic Capacities of PLD ~1995 Virtex-II 1000 Virtex-II 3000 Spartan-3 1000 Spartan-3 1000 Virtex-5 LX30 Virtex-5 LX30 Gates1 million3 million1 million2 million-- Flip- Flops 10,24028,67215,36040,96019,20028,800 LUTs10,24028,67215,36040,96019,20028,800 Multi- pliers 409624403248 Block RAM (kb) 720172843272011521728 Present FPGA Resource Specifications for XILINX Families Built-in PowerPC® Hard processor

18 Author’s name | Place, Month xx, 2007 | Event 18 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Major FPGA vendors SRAM-based FPGAs Xilinx Inc. – www.xilinx.comwww.xilinx.com Altera Corp.– www.altera.comwww.altera.com Atmel Corp.– www.atmel.comwww.atmel.com Lattice Semiconductor Corp. – www.latticesemi.comwww.latticesemi.com Antifuse and flash-based FPGAs Actel Corp. – www.actel.comwww.actel.com QuickLogic Corp. – www.quicklogic.comwww.quicklogic.com

19 Author’s name | Place, Month xx, 2007 | Event 19 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition The Programmable Marketplace The Programmable Marketplace Q1 Calendar Year 2005 Source: Company reports Latest information available; computed on a 4-quarter rolling basis Xilinx Altera Lattice Actel QuickLogic: 2% Xilinx All Others Two dominant suppliers, indicating a maturing market PLD SegmentFPGA Sub-Segment Other: 2% 51% 33% 5% 7% Altera 58% 31% 11%

20 Author’s name | Place, Month xx, 2007 | Event 20 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Benefits of FPGA Technology Performance (hardware parallelism, ) Time to market (Commercial off-the-shelf (COTS) hardware) Cost Reliability (No OS. Deterministic hardware dedicated to every task) Long-term maintenance

21 Author’s name | Place, Month xx, 2007 | Event 21 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Applications of FPGAs Digital signal processing, software-defined radio, aerospace, Defense system, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation glue logic for PCBs Full systems on chips (SoC) High performance computing (FFT or Convolution, massive parallelism)

22 Author’s name | Place, Month xx, 2007 | Event 22 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Timing Characteristics of Combinational Circuits Combinational Circuits Are Characterized by Propagation Delays through logic components (gates, LUTs) through interconnects (routing delays) t p LUT t p routing LUT Total propagation delay through combinational logic

23 Author’s name | Place, Month xx, 2007 | Event 23 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Timing Characteristics of Combinational Circuits (2) Total Propagation Delay of Logic Depends on the Number of Logic Levels and Delays of Logic Components Number of logic levels is the number of logic components (gates, LUTs) the signal propagates through Routing Delays Depend on: Length of interconnects Fanout

24 Author’s name | Place, Month xx, 2007 | Event 24 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Timing Characteristics of Combinational Circuits (3) Fanout – Number of Inputs Connected to One Output Each inputs has its capacitance Fast switching of outputs with high fanout requires higher currents and strong drivers LUT

25 Author’s name | Place, Month xx, 2007 | Event 25 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Timing Characteristics of Combinational Circuits (4) In Current Technologies Routing Delays Make 45-65% of the Total Propagation Delays

26 Author’s name | Place, Month xx, 2007 | Event 26 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Timing Characteristics of Sequential Circuits (1) Timing Features of Flip-flops Setup time t S – minimum time the input has to be stable before the rising edge of the clock Hold time t H – minimum time the input has to be stable after the rising edge of the clock Propagation delay t P – time to propagate input to output after the rising edge of the clock

27 Author’s name | Place, Month xx, 2007 | Event 27 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Timing Characteristics of Sequential Circuits (2) DQ clk D Q tStS tHtH tPtP Input D must remain stable during this interval Input D can freely change during this interval

28 Author’s name | Place, Month xx, 2007 | Event 28 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition FPGA Design Flow http://www.bitsim.com/fpga-design-flow.htm Register Transfer Level

29 Author’s name | Place, Month xx, 2007 | Event 29 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Hardware description languages Verilog VHDL System C System Verilog “Low Level” ( assembly)

30 Author’s name | Place, Month xx, 2007 | Event 30 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Introduction to VHDL Developed at the US Department of Defense Strongly-typed and is not case sensitive. IEEE standard 1076-1987 Allows to describe both the behavior of the required system AND the respective Testbench

31 Author’s name | Place, Month xx, 2007 | Event 31 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition VHDL CODE examples -- (this is a VHDL comment) -- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_1164.all; -- this is the entity entity ANDGATE is port ( IN1 : in std_logic; IN2 : in std_logic; OUT1: out std_logic); end ANDGATE; architecture RTL of ANDGATE is begin OUT1 <= IN1 and IN2; end RTL; architecture InputsOutputs

32 Author’s name | Place, Month xx, 2007 | Event 32 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition MUX in VDHL -- template 1: X <= A when S = '1' else B; -- template 2: with S select X <= A when '1' else B; -- template 3: process(A,B,S) begin case S is when '1' => X <= A; when others => X <= B; end case; end process; -- template 4: process(A,B,S) begin if S = '1' then X <= A; else X <= B; end if; end process; -- template 5 - 4:1 MUX, where S is a 2-bit std_logic_vector : process(A,B,C,D,S) begin case S is when "00" => X <= A; when "01" => X <= B; when "10" => X <= C; when others => X <= D; -- or when "11" end case; end process;

33 Author’s name | Place, Month xx, 2007 | Event 33 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Counter Example library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- for the unsigned type entity counter_example is generic ( WIDTH : integer := 32); port ( CLK, RESET, LOAD : in std_logic; DATA : in unsigned(WIDTH-1 downto 0); Q : out unsigned(WIDTH-1 downto 0)); end entity counter_example; architecture RTL of counter_example is signal cnt : unsigned(WIDTH-1 downto 0); begin process(RESET, CLK) begin if RESET = '1' then cnt '0'); elsif rising_edge(CLK) then if LOAD = '1' then cnt <= DATA; else cnt <= cnt + 1; end if; end process; Q <= cnt; end architecture RTL;

34 Author’s name | Place, Month xx, 2007 | Event 34 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Hierarchical design Top Design Component 1 Component 2 Component 3 VHDL allows a hierarchy of entities containing components. At each level VHDL allows multiple architectures and multiple configurations for each entity.

35 Author’s name | Place, Month xx, 2007 | Event 35 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition Hierarchical design in VHDL Hierarchical design: architecture STRUCT of INC is signal X,Y,S,C : bit; component HALFADD (defined in HALFADD.vhdl) port(A,B : in bit; SUM, CARRY : out bit); end component; begin U1: HALFADD port map (X,Y,S,C);(instance) -- other statements end STRUCT;

36 Author’s name | Place, Month xx, 2007 | Event 36 B.B. Carvalho | Lisbon, February 17, 2009 | Diagnostics & Data Acquisition

Download ppt "Instituto de Plasmas e Fusão Nuclear Instituto Superior Técnico Lisbon, Portugal B.B. Carvalho | Lisbon, February 16, 2009 |"

Similar presentations

Introduction to Programmable Logic John Coughlan RAL Technology Department Electronics Division.

Introduction to Programmable Logic John Coughlan RAL Technology Department Electronics Division.
Lecture 15 Finite State Machine Implementation

Lecture 15 Finite State Machine Implementation
Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.

Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.
Survey of Reconfigurable Logic Technologies

Survey of Reconfigurable Logic Technologies
Programmable Logic Devices

Programmable Logic Devices
FPGA Devices & FPGA Design Flow

FPGA Devices & FPGA Design Flow
History TTL-logic PAL (Programmable Array Logic)

History TTL-logic PAL (Programmable Array Logic)
Implementing Logic Gates and Circuits Discussion D5.1.

Implementing Logic Gates and Circuits Discussion D5.1.
Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.

Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.
02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.

FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.
The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA  What’s inside the chip? How does it implement random logic? What other features can you use?  What.

The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA  What’s inside the chip? How does it implement random logic? What other features can you use?  What.
Programmable logic and FPGA

Programmable logic and FPGA
1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
FPGAs and VHDL Lecture L13.1 Sections 13.1 – 13.3.

FPGAs and VHDL Lecture L13.1 Sections 13.1 – 13.3.
Multiplexers, Decoders, and Programmable Logic Devices

Multiplexers, Decoders, and Programmable Logic Devices
EET 1131 Unit 4 Programmable Logic Devices  Read Kleitz, Chapter 4.  Homework #4 and Lab #4 due next week.  Quiz next week.

EET 1131 Unit 4 Programmable Logic Devices  Read Kleitz, Chapter 4.  Homework #4 and Lab #4 due next week.  Quiz next week.
Programmable Array Logic (PAL) Fixed OR array programmable AND array Fixed OR array programmable AND array Easy to program Easy to program Poor flexibility.

Programmable Array Logic (PAL) Fixed OR array programmable AND array Fixed OR array programmable AND array Easy to program Easy to program Poor flexibility.
General FPGA Architecture Field Programmable Gate Array.

General FPGA Architecture Field Programmable Gate Array.
EET 252 Unit 5 Programmable Logic: FPGAs & HDLs  Read Floyd, Sections 11-5 to 11-10.  Study Unit 5 e-Lesson.  Do Lab #5.  Lab #5a due next week. 

EET 252 Unit 5 Programmable Logic: FPGAs & HDLs  Read Floyd, Sections 11-5 to  Study Unit 5 e-Lesson.  Do Lab #5.  Lab #5a due next week. 

Similar presentations

Ads by Google