1. 1 COMP541 Sequencing – III (Sequencing a Computer) Montek Singh April 9, 2007

2. 2 Test 2  On April 17  Covers Memories Memories Arithmetic Arithmetic Datapaths Datapaths Sequencing Sequencing

3. 3 Design Reviews: Last Week of Classes  Individual meetings during class time next week (and maybe one more day)  20 minutes  Please prepare a presentation Not necessarily a PPT, but don’t make up your description on the fly Not necessarily a PPT, but don’t make up your description on the fly

4. 4 Chapter 10-7  Simple computer architecture Not unlike MIPS, except 16 bits Not unlike MIPS, except 16 bits  Single-cycle hardwired control  Multicycle microprogrammed control

5. 5 Instruction Formats  Register-type instructions  Only 8 registers (3 bits)

6. 6Immediate  Only 3 bits for the immediate value (Op)  Mostly useful for typical increments/decrement Or just as an example Or just as an example

7. 7Branching  PC relative branching  The 6 bits are sign extended to 16  Opcode might specify branch on zero, if register SA is zero

8. 8 Example Instructions

9. 9 Contrast to Microoperations  Although appear similar, they’re not  Computer instructions fetched using PC  Branching much more general  Decoding of computer instructions usually more complex

10. 10Resources  Book implies Harvard architecture  Separate I and D  They treat I memory as ROM Asynchronous Asynchronous

11. 11 Single-Cycle Control  Datapath is same as example we used in datapath topic Next slide shows for review Next slide shows for review  First look at overall control  Then look at instruction decoder

12. 12 Datapath & Control Word

13. 13Arch Instruction Memory treated as ROM (combinational) 3 bits sent to ALU for immediate instructions Address offset sent for relative branch. Adder not shown (neither is PC increment). Branch control inputs are status from ALU and lines from decoder.

14. 14 Instruction Decoder  Many lines (the three regs) need no logic RISC Style RISC Style  Architecture tailored so parts of inst. correspond to control lines

15. 15Control  Not much more to say Simple, partly because decoding so straightforward Simple, partly because decoding so straightforward  Drawbacks Some instructions, like multi-cycle shifts, can’t be implemented w/o complex datapath Some instructions, like multi-cycle shifts, can’t be implemented w/o complex datapath Two memories (essentially a ROM and an async data memory) Two memories (essentially a ROM and an async data memory)  Two cycles needed to use one memory  Biggest problem is delay

16. 16 Delay in Single-Cycle Control  Worst case delay with reasonable components Say, total 17ns Say, total 17ns Could only clock at about 50 MHz Could only clock at about 50 MHz  Pipelining is a solution  First let’s look at multi-cycle control

17. 17 Multi-Cycle Hardwired Control  Goals Support more complex instructions Support more complex instructions Use single memory Use single memory  Not necessarily coupled with multi-cycle

18. 18Arch

19. 19 Instruction Register  IL – load signal for IR  PS, for PC control Hold value multiple cycles, increment, load, etc. Hold value multiple cycles, increment, load, etc.

20. 20 Single Memory  PC addresses memory  Mux M gates address  MM signal to select program/data address  Inst. stored in IR

21. 21 Added Temporary Regs  Now 16x16  8 not visible to user  New signals to address the registers

22. 22 Sequence Control

23. 23 Control Word

24. 24 Control Design  Not hard to specify state diagram Derived from definition of ISA Derived from definition of ISA  Hard to design logic manually  If didn’t have logic synthesis, would probably use microprogramming

25. 25 Two-Cycle Instructions  Simplest instructions have 2 cycles Fetch (instruction) Fetch (instruction) Execute Execute  This is minimum necessary  They assume async memory Don’t need extra clock cycles Don’t need extra clock cycles

26. 26 Basic Inst.

27. 27Branch  Test and modify PC

28. 28 Next Step  Make a table or write Verilog from ASM diagram and instruction descriptions  Tedious, but not hard  Same as you’ve done, with more details State machine easy for these instructions State machine easy for these instructions

29. 29 Table from ISA and ASM

30. 30 Load Register Indirect  Three cycles Temporary register used Temporary register used

31. 31Shift  Shift right/left multiple  R[SA] to be shifted  First tested for 0  R9 loaded with shift length

32. 32 Multi-Cycle Table

33. 33 Summary – multi-cycle  Multi-cycle computer enables more complex instructions  May also be faster  We’ll also briefly look at pipelined computers – more parallelism but more complex control

34. 34 Limits to Clock Period  Conventional datapath  12 ns delay, so maximum is 83 MHz clock  Maybe have even tighter constraints due to control logic

35. 35Pipelining  Break datapath into stages  Add registers between stages  Like production line – book uses car wash example Wash, rinse, dry Wash, rinse, dry

36. 36 Latency vs Throughput  Latency, the amount of time it takes to execute an instruction, does not improve In fact, typically increases In fact, typically increases  Throughput, the number of instructions executed per second, increases By almost the number of pipeline stages By almost the number of pipeline stages

37. 37 Expected Performance  Longest stage is 5ns  So clock can be 200 MHz  Not 3 x 83 MHz. Why?  Latency is 15ns  Also extra hardware

38. 38Datapath  3 Stages Operand Fetch Operand Fetch Execute Execute Write Back Write Back  Note that WB register is the register file (same as at top)

39. 39 Pipelined Execution  Note pipeline fill and empty  Efficiency is not 100%  Important to not stall pipeline