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Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 313 - Computer Organization Lecture 22 - Input/Output Fall 2004 Reading: Ch. 8 (Skim) Portions of these slides are derived from: Textbook figures © 1998 Morgan Kaufmann Publishers all rights reserved Tod Amon's COD2e Slides © 1998 Morgan Kaufmann Publishers all rights reserved Dave Patterson’s CS 152 Slides - Fall 1997 © UCB Rob Rutenbar’s 18-347 Slides - Fall 1999 CMU other sources as noted
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ECE 313 Fall 2004Lecture 22 - Input / Output2 Roadmap for the term: major topics Overview / Abstractions and Technology Instruction sets Logic & arithmetic Performance Processor Implementation Single-cycle implemenatation Multicycle implementation Pipelined Implementation Memory systems Input/Output
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ECE 313 Fall 2004Lecture 22 - Input / Output3 Outline - Input-Output Overview I/O Performance Metrics Types and Characteristics of I/O Devices Buses Interfacing I/O Devices
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ECE 313 Fall 2004Lecture 22 - Input / Output4 Overview - Input Output I/O is a critical part of computer systems I/O has greater impact as processor performance increases (remember Amdahl’s law?) Figure 8.1 Cache Memory - I/O Bus Processor Main Memory I/O Controller I/O Controller I/O Controller Disk Graphics Network Interrupts
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ECE 313 Fall 2004Lecture 22 - Input / Output5 Measuring I/O Performance Individual transactions Response time (Latency) Bandwidth (Throughput) How much data can move through system in given time? … OR How many I/O operations can we do per unit time? Overall Performance - Benchmarks for Supercomputer I/O Transaction Processing File System I/O Appropriate measure depends on application
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ECE 313 Fall 2004Lecture 22 - Input / Output6 Characterizing I/O Devices I/O Device Characteristics Behavior: input only, output only, or storage Partner: who or what is using the interface? Machine? Human Being? Data Rate: peak rate of data transfer Typical I/O Devices: See Fig. 8.2, p. 568, old p. 644
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ECE 313 Fall 2004Lecture 22 - Input / Output7 Hard Disk Components Image Source: Seagate Technolgy LLC www.seagate.com Platters Spindle Arm Actuator Interface Connector (SCSI or EIDE) Electronics Head
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ECE 313 Fall 2004Lecture 22 - Input / Output8 Hard Disk Organization Platters (2 sides each) Track Sector Typical numbers (depending on the disk size): 500 to 2,000 tracks per surface 32 to 128 sectors per track A sector is the smallest unit that can be read or written Traditionally all tracks have the same number of sectors: Outer tracks record at lower bit density than inner tracks Recent change: constant bit density, data rate varies with track
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ECE 313 Fall 2004Lecture 22 - Input / Output9 Hard Disk Performance Factors Seek Time move head to desired track today’s drives: 5-15ms Rotational Latency today’s drives: 5400-12,000RPM average: 0.5 * ( 1 / RPM ) Transfer Time time to transfer a sector (1KB) today’s drives: 10-30MB/Sec Controller Time Overhead from on-drive electronics added value: caching, prefetching Sector Track Head Platter Cylinder
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ECE 313 Fall 2004Lecture 22 - Input / Output10 Hard Disk Examples Characteristics IBM 3090 IBM UltraStarIntegral 1820 Disk diameter (inches) 10.88 3.50 1.80 Formatted data capacity (MB)22,700 4,300 21 MTTF (hours)50,000 1,000,000 100,000 Number of arms/box 12 1 1 Rotation speed (RPM) 3,600 7,200 3,800 Transfer rate (MB/sec) 4.2 9-12 1.9 Power/box (watts) 2,900 13 2 MB/watt 8 102 10.5 Volume (cubic feet) 97 0.13 0.02 MB/cubic feet 234 33000 1050 See also book Fig. 8.4
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ECE 313 Fall 2004Lecture 22 - Input / Output11 Buses Goal: connect I/O Devices to Processor, Memory Use shared wires for economic reasons Challenging design problem due to physical constraints length of bus number of devices Buses are specialized depending on purpose Processor-Memoryshort / high-speed Backplanemed. length / med. speed I/Olong / low speed
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ECE 313 Fall 2004Lecture 22 - Input / Output12 Buses Cache Processor Main Memory I/O Controller I/O Controller I/O Controller Disk Graphics Network Control Data Bus Structure Bus Operation Control signals - used to start a transaction (input/output) Data signals - used to transmit data (including addresses)
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ECE 313 Fall 2004Lecture 22 - Input / Output13 Bus Variations Synchronous vs. Asynchronous Single master vs. multiple masters Narrow vs. wide Long vs. short
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ECE 313 Fall 2004Lecture 22 - Input / Output14 Example Buses Processor / Memory Proprietary microprocessor buses - Max bandwidth 422 MByte/sec Backplane PCI - Max bandwidth 133 MByte/sec ISA (obsolete, but still there in many systems) I/O SCSI - Max bandwidth 40 MByte/sec (60MByte/sec for 2.0) USB - Max bandwidth 12 MByte/sec FireWire (IEEE 1394) - Max bandwidth 50 Mbyte/sec (100MByte/sec for Firewire 800)
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ECE 313 Fall 2004Lecture 22 - Input / Output15 Example - Buses on a Modern PC See also book Fig. 8.11-8.12
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ECE 313 Fall 2004Lecture 22 - Input / Output16 Interfacing I/O - Processor-Device Communication Processor accesses registers in device Control Register Status Register Data Register Connection styles Memory-Mapped I/O registers mapped to memory locations accessed using load/store I/O Instructions registers mapped to “device numbers” accessed using I/O instructions Processor Device Data Status Control
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ECE 313 Fall 2004Lecture 22 - Input / Output17 Interfacing I/O - Processor-Device Communcation Communicating w/ Processor Polling processor checks device status register problem: wastes processor time Interrupt-Driven I/O - initiated by device device interrupts processor processor interrupt handler processes input often combined with buffering Direct Memory Access (DMA) Device takes over bus for block transfer Device interrupts processor when complete Cache issues: what if we transfer memory that’s stored in cache?
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ECE 313 Fall 2004Lecture 22 - Input / Output18 I/O Summary I/O has growing impact on performance Wide range of I/O devices Buses provide pathways for I/O connection Software ultimately has to deal with I/O, too
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