1. E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Mon Oct 6 th Floorplan again Structural Verilog Secure Electronic Voting Terminal

2. Structural Verilog Entire System Enriched Floorplan Just doing it? Status Update

3. Data Bus Machine Init FSM User ID FSM Selectio n FSM Confirm ation FSM Display User ID SRAM Message ROM Card Reader Fingerprint Scanner Encryption Key SRAM User Input Write-in SRAM Choice SRAM TX_Check Selection Counter Key Register XOR 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder XOR 8 bit MUX 01 01 01 8 bit Add/Sub 01 8 bit MUX T: 128 8-bit REG T: 88 8-bit REG COMMS Register Shift Regist er In Shift Regist er Out constant init

4. Stealing From the Past ● For our size estimates we look at an SRAM cell from the Sprinkler Buddy Project ● Their cells were (4.32um x 7.92um) ● Therefor our 64x8 cell block of write- in SRAM would be: (34.56um x 506.88um) ● Since this aspect ratio would not work (even cut in half) We are going to assume the same area per cell (34.21um 2 ) but more square (5.22um x 6.57um)

5. SRAM Sizing ● The cells of the write in SRAM are split into two blocks ● The other SRAMs are whole ● The SRAMs are size with consideration given to the row decoders and the column enable/ tristates ● The row decoder size is based on a transistor density of.3 t/um

6. SRAM Placement ● The SRAMs are placed first, since their dimensions constrain the project ● The placement is set up to enhance the layout of the databus by putting the SRAM data lines close to each other ● The Key SRAM is isolated since it will have limited presence on the databus

7. DATA Bus ● Every connection to the data bus needs a gate (sometimes also a tri-state for bidirectional connections) ● The SRAMs already have this gate built into their logic. ● Other than routing, the only physical manifestation of the data bus will be a few t-gate based gates on the message rom, user input, tx-check and selection counter

8. Comms Block Bitslicing Key Regis ter XOR XOR 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder XOR XOR 8 bit MU X 01 010 8 bit Add/Su b 01 8 bit MU X 8 - b it R E G T: 88 8 - b it R E G COMMS Register Shi ft Re gist er In Shi ft Re gist er Ou t consta nt init MUXMUX REG FA XORXOR XORXOR MUXMUX MUXMUX REG The FA and REG are approx 6um x 6um The bitslice is 6um x 63um The key register will be a separate block The remaining blocks (Delta Sum Accumulator) will be manifested as an adder with 8 register and will be put along the bottom of the COMMs block being approximately 2 rows in size. (12um x 63um) The final COMMs block is 60umx63um Delta Sum accumulator

9. Comms Placement ● We can use the width of the Comms Block to force the last dimension on the layout ● The key register is placed to fill the gap beside the Key SRAM

10. Floorplan ● The aspect ratio is 2:1 ● The FSMs are grossly oversized to fill the excess space left beside the SRAMS ● We can make the FSM size more realistic by creating a wider/shorter SRAM cell

11. Floor Plan with Interconnects ● The interconnects travel heavily over the FSM ● These are mostly 1 bit enable signals and some are address lines ● The address lines (as well as the data bus) may need to be buffered ● Some internal connections are shown for the COMMs

12. Structural Verilog (simulations)