1. 8/18/05ELEC 5970-001/6970-001 Lecture 11 ELEC 5970-001/6970-001 (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Introduction Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 8/18/05ELEC 5970-001/6970-001 Lecture 12 Course Objective Low-power is a current need in VLSI design. Learn basic ideas, concepts and methods. Gain hands-on experience.

3. 8/18/05ELEC 5970-001/6970-001 Lecture 13 Low-Power Design Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. General topics –Algorithms and architectures –High-level and software techniques –Gate and circuit-level methods –Power estimation techniques –Test power

4. 8/18/05ELEC 5970-001/6970-001 Lecture 14 VLSI Chip Power Density 4004 8008 8080 8085 8086 286 386 486 Pentium® P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

5. 8/18/05ELEC 5970-001/6970-001 Lecture 15 Specific Topics on Low-Power Power dissipation in CMOS circuits Device technology –Low-power CMOS technologies –Energy recovery methods Circuit and gate level methods –Logic synthesis –Dynamic power reduction techniques –Leakage power reduction System level methods –Microprocessors –Arithmetic circuits –Low power memory technology Test Power Power estimation

6. 8/18/05ELEC 5970-001/6970-001 Lecture 16 Power in a CMOS Gate V DD i DD (t) Ground

7. 8/18/05ELEC 5970-001/6970-001 Lecture 17 Power Dissipation in CMOS Logic (0.25µ) %75%5%20 P total (0→1) = C L V DD 2 + t sc V DD I peak + V DD I leakage CLCL

8. 8/18/05ELEC 5970-001/6970-001 Lecture 18 Power and Energy Instantaneous power (Watts) P(t) = i DD (t) V DD Peak power (Watts) P peak = Max {P(t)} Average power (Watts) P av = [ ∫ 0 T P(t) dt ]/T Energy (Joules) E = ∫ 0 T P(t) dt

9. 8/18/05ELEC 5970-001/6970-001 Lecture 19 Components of Power Dynamic –Signal transitions Logic activity Glitches –Short-circuit Static –Leakage

10. 8/18/05ELEC 5970-001/6970-001 Lecture 110 Power of a Transition V DD Ground C R R Power = CV DD 2 /2

11. 8/18/05ELEC 5970-001/6970-001 Lecture 111 Logic Activity and Glitches 4 5 7 6 1 2 3 d=2 d=1

12. 8/18/05ELEC 5970-001/6970-001 Lecture 112 Low-Power Design Techniques Circuit and gate level methods – Reduced supply voltage – Adiabatic switching and charge recovery – Logic design for reduced activity – Reduced Glitches – Transistor sizing – Pass-transistor logic – Pseudo-nMOS logic – Multi-threshold gates

13. 8/18/05ELEC 5970-001/6970-001 Lecture 113 Low-Power Design Techniques Functional and architectural methods –Clock suppression –Clock frequency reduction –Supply voltage reduction –Power down –Algorithmic and Software methods

14. 8/18/05ELEC 5970-001/6970-001 Lecture 114 Test Power Power grid on a VLSI chip is designed for certain current capacity during functional operation: –Average current → heat dissipation –Peak current → noise, ground bounce Problem – Tests like scan or BIST are nonfunctional and may cause higher than the functional circuit activity; a functionally good chip can fail the test.

15. 8/18/05ELEC 5970-001/6970-001 Lecture 115 Power Estimation Methods Spice: Accurate but expensive Logic-level –Event-driven simulation –Statistical –Probabilistic High-level: Hierarchical

16. 8/18/05ELEC 5970-001/6970-001 Lecture 116 Student Evaluation Homework (30%) – almost 1/week Class Project (30%) Student presentation (10%) Final Exam (30%)