1. LOGO An Analog PLL-based Technique for VCO Phase Noise Reduction D. Mavridis, D.Karadimas, M. Papamichail, K.Efstathiou, G.Papadopoulos University of Patras, Greece

2. www.themegallery.com Company Logo 2 Contents Phase Noise Reduction by Frequency Synthesizers. 1 Analysis of the Technique 2 Simulation Results 3 Conclusion 4 An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

3. www.themegallery.com Company Logo 3 VCO’s Phase Noise Reduction in Frequency Synthesizers  Control Variable is the Phase  Phase Noise reduction due to the negative feedback An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

4. www.themegallery.com Company Logo 4 Phase Noise Reduction by PLL Increasing ω n : (++) Phase Noise reduction increases (- - ) Spurs increase (1) (2) An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

5. www.themegallery.com Company Logo 5 Key point  Increase Sampling rate:  Phase Information over a wide Bandwidth  Quantization Noise at very high frequencies  Large ω n values can be obtained => Increased Phase Noise Reduction An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

6. www.themegallery.com Company Logo 6 Block Diagram Variable Mapping Freq. SynthesizerCCO Fstep (Hz)Iref(A) Φstep (rad)∫Iref Fout( Hz) Φout (rad) (1) (2) (3) (4) (5) An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

7. www.themegallery.com Company Logo 7 CCO dynamics Transfer Function (1) (2) (3) An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

8. www.themegallery.com Company Logo 8 Properties of the CCO  Very high sampling rate of the VCO’s phase  Reject the VCO’s Phase Noise for a wide bandwidth  Increased Phase Noise Rejection  CCO’s gain is not dependent on VCO’s gain  Fast response  CCO ->VCO using a simple transconductance An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

9. www.themegallery.com Company Logo 9 Simulation Setup Technology: AMS035 – CMOS Noisy VCO: Ring Oscillator (1) (2) (3) An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

10. www.themegallery.com Company Logo 10 Simulation Results Free Run VCO ζ=0.7 f n =20MHz,Np=4 fsample=250MHz ζ=0.5 f n =20MHz, Np=4 fsample=250MHz ζ=0.5 f n =40MHz, Np=2 fsample=500MHz An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

11. www.themegallery.com Company Logo 11 Conclusion  Technique based on PLL  Negligible circuitry  Small Power overhead  Small chip area An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al.

12. LOGO Thank you for your attention!