1. Microprocessors & Embedded Systems
DIGITAL II
Microprocessors & Embedded Systems
ECE
Week 3
Custom Single Purpose
Processors: Hardware
Note: Certain parts of this presentation have been intentionally left blank or missing for you to complete during or after the class
Robi Polikar, Ph.D.
John L. Schmalzel, P.E., Ph.D.

2. Chapter 2: Custom single-purpose processors
Outline
Chapter 2: Custom single-purpose processors
Introduction
Combinational logic
Sequential logic
Custom single-purpose processor design
RT-level custom single-purpose processor design

3. Digital Foundations
The basic model of a computer system:
CPU
MEM
I/O

4. Central Processing Unit (CPU)
MEM
I/O

5. Memory
CPU
MEM
I/O

6. Input/Output (I/O)
CPU
MEM
I/O

7. Hierarchical View of EP and Digital Systems
CPU
MEM
I/O
Operating System
HLLs
Computer Architecture
State Machines
Interface Method
Design Techniques
MSI Functions
Boolean Algebra
Gates

8. Introduction Processor A custom single-purpose processor may be
Digital circuit that performs a computation tasks
Controller and datapath
General-purpose: variety of computation tasks
Single-purpose: one particular computation task
Custom single-purpose: non-standard task
A custom single-purpose processor may be
Fast, small, low power
But, high NRE, longer time-to-market, less flexible
Microcontroller
CCD preprocessor
Pixel coprocessor
A2D
D2A
JPEG codec
DMA controller
Memory controller
ISA bus interface
UART
LCD ctrl
Display ctrl
Multiplier/Accum
Digital camera chip
lens
CCD

9. CMOS transistor on silicon
The basic electrical component in digital systems
Acts as an on/off switch
Voltage at “gate” controls whether current flows from source to drain
Don’t confuse this “gate” with a logic gate
gate
source
drain
Conducts
if gate=1
source
drain
oxide
gate
IC package IC
channel
Silicon substrate 1

10. CMOS transistor implementations
Complementary Metal Oxide Semiconductor
We refer to logic levels
Typically 0 is 0V, 1 is 5V
Two basic CMOS types
nMOS conducts if gate=1
pMOS conducts if gate=0
Hence “complementary”
Basic gates
Inverter, NAND, NOR
gate
source
drain
nMOS
Conducts
if gate=1
gate
source
drain
pMOS
Conducts
if gate=0

11. Basic logic gates x F 1 x y F 1 x y F 1 x y F 1 F = x Driver F = x y1 F x y x y F 1 F y x x y F 1 x y F x y F 1
F = x
Driver
F = x y
AND
F = x + y OR
F = x  y
XOR x F x F 1 x y F x y F 1 x y F x y F 1 x y F x y F 1
F = x’
Inverter
F = (x y)’
NAND
F = (x+y)’
NOR
F = x y
XNOR

12. Combinational logic design Summary
B) Truth table
A) Problem description
y is 1 if a is to 1, or b and c are 1. z is 1 if b or c is to 1, but not both, or if all are 1.
C) Output equations y=
z =
Inputs
Outputs a b c y z 1 1 1 1 1 1 1 1 1
D) Minimized output equations 1 1 1 00 1 01 11 10 a bc y
y =
E) Logic Gates a y b c 00 1 01 11 10 z
z = a bc z

13. RT Level Combinational components
Multiplexer Decoder Adder Comparator ALU
log n x n
Decoder … O1 O0
O(n-1) I0
I(log n -1)
n bit,
m function
ALU n A B … S0
S(log m) O
n-bit
Adder n A B
sum
carry
n-bit
Comparator n A B
less
equal
greater
n-bit, m x 1
Multiplexer O … S0
S(log m) n
I(m-1) I1 I0
O =
I0 if S=0..00
I1 if S=0..01 …
I(m-1) if S=1..11
O0 =1 if I=0..00
O1 =1 if I=0..01 …
O(n-1) =1 if I=1..11
sum = A+B
(first n bits)
carry = (n+1)’th
bit of A+B
less = 1 if A<B
equal =1 if A=B
greater=1 if A>B
O = A op B
op determined
by S.
With enable input e  all O’s are 0 if e=0
With carry-in input Ci
sum = A + B + Ci
May have status outputs carry, zero, etc.

14. D-type Sequential Circuits Include feedback Presence of a clock
Behavior is no longer simply a function of the inputs--must be evaluated synchronously with clock
Flip-flops
D-type
J-K type
S-R type
etc.

15. D-F/F P C Dn Qn+1 1 0 1 X 1 1 1 1 0 X 1 1 0 0 0 X Illegal P D Q CK Q* X X
Illegal P D Q CK Q*
Excitation Function: Dn = Qn+1 C

16. State Machines Mealy: Outputs depend on states and on inputs.
Moore: Outputs depend only on states.
One-Hot: A type of Moore machine in which there is one F/F per state.

17. Combinatorial Network
State Machine Models
Moore Outputs
State Memory
(& One-Hot)
Clk
Combinatorial Network
Mealy Outputs
Inputs

18. Sequential Circuit Design
Problem statement
State diagram
Transition table
Simplified excitation functions
Implementation
Verification

19. Example
Design a sequence detector that will identify 1011. SM
1011 Z

20. State Diagram Input/Output Input Input/Output Input Moore Mealy Name

21. One-Hot SMs
Moore machines are glitchless since outputs change only synchronously with clock.
For relatively small numbers of states, techniques of F/F minimization are largely counterproductive with available “sea-of-gates” FPGA.
A 12-state SM: Don’t bother to reduce/encode.
A 16-bit counter: Definitely encode states.

22. SM for 1011 Sequence Detector
Reset 1 1
Found
None
Found1 1
Found4 Z
Found2 1 1
Found3
Note: Dashed lines show non-resetting algorithm.

23. Transition Table Output Present State Input Next State
Z F0 F1 F2 F3 F X F0’ F1’ F2’ F3’ F4’

24. Excitation Functions
The Transition Table could be large: 26 = 64, but since this is a One-Hot SM, there can be only one state active at a time. When writing the BA for each excitation function, listing the complemented states is redundant.
For example: DF0 = F0•X* + F2•X*, instead of
DF0 = F0•F1*•F2*•F3*•F4*•X* + F0*•F1*•F2•F3*•F4*• X*
Similarly,
DF1 = F0•X + F1•X + F4•X
DF2 = F1•X* + F3•X* + F4•X*
DF3 = …..
DF4 = …….

25. Simplification
If there are any redundant terms, we can simplify; however, for One-Hot approach, there are no simplifications possible since we must account for every separate state path using a separate FF.

26. Implementation
Assign one D-F/F per state and complete the combinatorial network required for each input. Implementation of F0 is shown:
Clk
& + D Q F0 F2 X* P
The final network output, Z = F4. For reset, use asynchronous F/F inputs: Preset F0 and clear F1-F4.

27. Verification Check that the SM performs as required.
More complex input vectors are required since the internal state memory expands total possible states.
Use simulation tools.

28. The Power of One-Hot Design
Can skip transition table--“read” the implementation directly off the state diagram: 1 1
Found
None
Found1 F0
& + D Q X F1 F1 X C
Clk

29. Sequential Circuit Functions
Counters
Binary, BCD
Ripple, Synchronous
Registers and Latches
PIPO, PISO, SIPO, SISO

30. Sequential components
clear
n-bit
Register n
load I Q
count
shift I Q
n-bit
Shift register
n-bit
Counter n Q
clear
Q =
0 if clear=1,
I if load=1 and clock=1,
Q(previous) otherwise.
Q = lsb
- Content shifted
- I stored in msb
Q =
0 if clear=1,
Q(prev)+1 if count=1 and clock=1.

31. Sequential logic design Summary
A) Problem Description
You want to construct a clock divider. Slow down your pre-existing clock so that you output a 1 for every four clock cycles

32. Sequential logic design (cont.)
E) Minimized Output Equations
F) Combinational Logic a Q1 Q0 I0 I1 x