1. 5 Feb 2007 Waclaw Karpinski 1 PEBS Electronics W. Karpinski I. Physikalisches Institut Aachen, 10 January 2007

2. 5 Feb 2007 Waclaw Karpinski 2 Outline An overview of the PEBS Electronics Subdetector Readout: - TRD - Tracker - ECAL - ToF - TGB (Trigger Box) Summary

3. 5 Feb 2007 Waclaw Karpinski 3 PEBS Electronics

4. 5 Feb 2007 Waclaw Karpinski 4 AMS Electronics

5. 5 Feb 2007 Waclaw Karpinski 5 16 layers, 7 chambers/layer =112 chambers 16 “straw tubes” per chamber 1792 channels in total the readout schema could be the same as in AMS2 the available spare boards can be used in PEBS-TRD readout PEBS -TRD

6. 5 Feb 2007 Waclaw Karpinski 6 UFE= front end UTE= tube end UHVD= high voltage distribution UPSFE= power supply for UFE UDR= data reduction board JINF= interface board for higher DAQ UHVG= high voltage generator AMS2-TRD Readout

7. 5 Feb 2007 Waclaw Karpinski 7 U-Crate UPD UDR2UPSFEJINF UHVG AMS2-TRD Readout not available for PEBS

8. 5 Feb 2007 Waclaw Karpinski 8 VA 1 VA 2 12 bit ADC AD7476 Hybrid Control Circuit & Logic Unit DC shift V  S SB H HB +2.0 A -2.0 A GND +2.0 D -2.0 D ESD-Protection IC and Network Ch 1 - 32 Ch 33 - 64 Airborn Connectors MA231-032-125-5000 Dreset1, Dreset6, ShiN1, ShiN2, CLK_FF, Dreset5, hold, hold_b, test_on CAL +2.0 A -2.0 A + - - + SDATA+ SDATA- SCLK+ SCLK- +2.0 D -2.0 D +2.0 D -2.0 D Micro D-Sub Connector 21 pol. Schematic Diagram of UFE Front-End Electronics : UFE

9. 5 Feb 2007 Waclaw Karpinski 9 Data Reduction UDR2 Hot Side Gate Array DSP Analog::Digital Isolation Barrier 7x 64x IN OUT Cold Side Performs: buffering of the raw data data reduction in the DSP data transmission to the Global DAQ Digitized Data

10. 5 Feb 2007 Waclaw Karpinski 10 Equipment needed: 28x UFE, 4x UDR, 2x UPSF, 4xUHVD, 1x C&DI TRD Power Consumption = UFE(7W) + Ucrate(13W) + UPD(11W) =31W Structure of the PEBS -TRD Readout

11. 5 Feb 2007 Waclaw Karpinski 11 PEBS -TRD CRATE UDR -data reduction board UPSFE -power supply for UFE C&DI - interface for higer DAQ UHVD - high voltage generator

12. 5 Feb 2007 Waclaw Karpinski 12 4 disks á 46 modules = 184 Modules SiPMreadout using SiPM arrays with 32 strips 4 SiPM arrays on each module end  two Front End Hybrids/module á 128 channels in total 47104 channels PEBS -Tracker SiPM arrays arrangement of the SiPM arrays on the module end SiPM array with 16 channels

13. 5 Feb 2007 Waclaw Karpinski 13 SiPMSiPM specifications - channel size: 1 mm x 0.25 mm - pixel size: 0.043 x 0.043 mm 2 = 135 pixels/channel  8 bit ADC - operating voltage: ~ 40V - gain = 0.8 x 10 6  preamplifier with large dynamic range necessary - SiPM gain varies with bias voltage: 40% / 1V Do we need gain adjustment for individual channels ? If yes, it must be implemented on chip level (DAC)  new chip design necessary  significant increase of cost and development time - dark current =500 nA/channel - dark count ~.5 MHz (40V, T=22°C)  fast shaping time required to reduce pile up  ac coupling between detector and preamplifier or active leakage current compensation on the chip PEBS -Tracker

14. 5 Feb 2007 Waclaw Karpinski 14 SiPM- Behaviour Temperature depandance from Nakamura (KOBE) (7th ACFA workshop on Physics and Detector at the Linear Collider) gain shift by 1.5% /°C gain variations with bias voltage by 80%/1V increase of noise rate by factor of 70%/10°C  the operation temperature of SiPM should be well controlled  the operation temperature should be low  precise voltage control for good gain stability

15. 5 Feb 2007 Waclaw Karpinski 15 ROCs possibly adequate for SiPM signal processing

16. 5 Feb 2007 Waclaw Karpinski 16 MAROC : 64 ch MAPMT chip for ATLAS lumi Characteristics 64 PMT channels input (50-100 Ω) Variable gain current conveyor (0-2) 6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16 64 discriminator outputs (GTL) 100% sensitivity to 1/3 photoelectron (50fC). Counting rate up to 2 MHz Common threshold loaded by internal 10bit DAC 1 multiplexed charge output with variable shaping 20-200ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pC) Crosstalk < 1% Technology : AMS SiGe 0.35µm Submitted 13 june 05 Area 12 mm 2 Dissipation 130 mW @ VDD=3.5V Synoptic diagramm of MAROC1 Hold signal Variab le Gain Pream p. Variable Slow Shaper S&H Bipolar Fast Shaper 64Trigger outputs Gain correction 6 bits/channel discriminator threshold 10 bits DAC Multiplexed charge output 64 PM inputs 10 bit DAC ©N. Seguin (LAL)

17. 5 Feb 2007 Waclaw Karpinski 17 ILC SiPM Chip 18-channel 8-bit DAC (0-5V) 18-channel front-end readout : Variable gain charge preamplifier (0.67 to 10 V/pC) Variable shaping time CRRC2 shaper (12 to 180 ns) Track and hold  1 multiplexed output Power consumption : ~200mW (supply : 0-5V) Technology : AMS 0.8 m CMOS Chip area : ~10mm² Package : QFP-100

18. 5 Feb 2007 Waclaw Karpinski 18 Channel architecture for SiPM readout 100nF 10pF Charge Preamplifier :  Low noise : 1300e- @40ns  Variable gain : 4bits : 0.67 to 10 V/pC CR-RC² Shaper : Variable time constant : 4 bits (12 to 180ns) 12ns  photoelectron measurement (calibration mode) 180ns  Mip measurement (physics mode) compatibility with ECAL read-out 12kΩ 4kΩ 24pF 12pF 3pF in 8pF4pF2pF1pF 40kΩ 8-bit DAC 0-5V ASIC Rin = 10kΩ 50Ω 100MΩ 2.4pF 1.2pF 0.6pF 0.3pF 0.1pF 0.2pF 0.4pF 0.8pF 6pF

19. 5 Feb 2007 Waclaw Karpinski 19 Prospective for A-HCAL SiPM Chip Similar developments for AHCAL Chip fully dedicated to SiPMs Internal DAC for SiPM gain adjustment (5V range) Auto-trigger (fast shaper + Discriminator) Internal TDC, 1 ns step Internal 12 bit ADC Power pulsing T&H x1 Variable gain Preamplifier Discri TDC 12-bit ADC 8 bit DAC (0-5V) in Fast Shaper Shaper t p ~30-40ns Auto-trigger 12-bit DAC Threshold Capacitance for AC coupling … Analogue Memory Charge Ouput Time Ouput

20. 5 Feb 2007 Waclaw Karpinski 20 PEBS-Tracker Readout FE Hybrid consists of: - biasing network - 2 VA64 chips - 1 amplifier - readout control - expected power consumption 2 mW / channel - readout time ~85 µs/event FE-Hybrid Ver.2

21. 5 Feb 2007 Waclaw Karpinski 21 Tracker Front-End Hybrid SiPMs Arrays Biasing & AC coupling VA64-chip

22. 5 Feb 2007 Waclaw Karpinski 22 Data Reduction TDR2 Boards +80V Gate Array DSP 2x ADC ADC Analog::Digital Isolation Barrier 640x IN 384x IN OUT TDR2 The readout of PEBS-Tracker can be realized using modified TRD2 boards from AMS Architecture - on FE-Hybrid analog signal processing only - TRD2 performs digitization calibration and data reduction for 2048 channels 6 analogue inputs and 6 ADCs per board Analog Receivers Data Reduction Data Compresion

23. 5 Feb 2007 Waclaw Karpinski 23 PEBS-Tracker Readout 16 FE-Hybrids á 128 channels connected to 1 TDR =2048 channels/TDR 368 FEHs, 23 TDRs and 2 crates á 12 TRDs necessary for Tracker readout Power consumption: 85W on FEHs +94W in TDRs +47W in PSs = 226W

24. 5 Feb 2007 Waclaw Karpinski 24 PEBS-Tracker Crate TDR -data reduction board TPSFE -power supply for Front End C&DI - interface for higer DAQ TBIAS - bias voltage generator

25. 5 Feb 2007 Waclaw Karpinski 25 PEBS ECAL Electronics 80 Layers, 95 modules/layer Two modules will be readout by one SiPM  3800 channels in total Readout using SiPMs with the size 3mm x 3mm, ~8100 pixels / SiPM The same readout architecture as for the PEBS-Tracker Could be the same ASIC (VA64-SiPM) SiPM 3 mm

26. 5 Feb 2007 Waclaw Karpinski 26 PEBS ECAL Electronics Front-End Board with 6 VA64-SiPM chips One board collects the signals from one side of 2 super layers = 384 channels 5 Front-End Boards controlled by 1 modified TRD board = 1920 channels/TDR Power consumption: 7 W on FEHs +8 W in TDRs + 4 W in PSs = 19 W

27. 5 Feb 2007 Waclaw Karpinski 27 PEBS-ECAL Crate EPSFE -power supply for Front End EBIAS - bias voltage generator TDR -data reduction board C&DI - interface for higer DAQ

28. 5 Feb 2007 Waclaw Karpinski 28 Scintillator Electronics 4 ToF planes á 8 scintillator paddles 32 scintillators in total with -(4 SiPMs ) per end  256 channels or -one PM per end  64 PMs in totalProvides: fast (~30ns) coincidence between at least 3 out of 4 ToF planes to select particles within the main PEBS acceptance measurement of the particle velocity including the direction of the particle, (resolution of 100ps) measurement of the absolute charge of particles rejection of protons with E<1GeV at the trigger level

29. 5 Feb 2007 Waclaw Karpinski 29 PM vs SiPM High Voltage (2000V) Influenced by magnetic fields Influenced by vibrations Fragile and heavy Low noise Good temperature stability Better gain stability Low voltage (30V-60V) Tested up to 4 Tesla Not influenced by vibrations Light and robust High noise Sensitive to temperature variation Gain sensitive to voltage variation

30. 5 Feb 2007 Waclaw Karpinski 30 TOF Readout in AMS2 for 24 PMTs (20 ToF and 4 ACC ) consists of: SDR2 - SDR2: data collection and reduction & slow control 4 x SFET2 - 4 x SFET2: charge and time measurement of TOF anodes (5 PMs/ board) SFEA2 - SFEA2: charge and time of ACC SFEC - SFEC: dynode charge SPT2 - SPT2: pre-trigger unit fast trigger input TSPD - TSPD: DC/DC converters SHV - SHV: high voltage box AMS2 Scintillator Electronics

31. 5 Feb 2007 Waclaw Karpinski 31

32. 5 Feb 2007 Waclaw Karpinski 32 PM-PEBS Scintillator Electronics TOF Readout in PEBS for 64 PMTs will consist of three crates: 1 xSDR2 - 1 x SDR2: data collection and reduction & slow control 5 x SFET2 - 5 x SFET2: charge and time measurement TOF anodes (5 PMs/ board) 1 xSPT2 - 1 x SPT2: pre-trigger unit, fast trigger input 3 xSHV boxes: - 3 x SHV boxes: high voltage generator 3 xTSPD - 3 x TSPD: DC/DC converters SHV-Box TSPD

33. 5 Feb 2007 Waclaw Karpinski 33 Potential ROCs for ToF with SiPms

34. 5 Feb 2007 Waclaw Karpinski 34 OPERA_ROC (2002) 32 channels Variable gain preamp Autotrigger on ¼ p.e. BiCMOS 0.8µ 3 000 chips 64 ch front-end board (BERN) ASIC production for OPERA target tracker (S. Blin, T. Caceres, CdLT, G. Martin, L. Raux) Readout ASIC for multi-anode Photomultiplier (Hamamatsu)

35. 5 Feb 2007 Waclaw Karpinski 35 MAROC : 64 ch MAPMT chip for ATLAS lumi Characteristics 64 PMT channels input (50-100 Ω) Variable gain current conveyor (0-2) 6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16 64 discriminator outputs (GTL) 100% sensitivity to 1/3 photoelectron (50fC). Counting rate up to 2 MHz Common threshold loaded by internal 10bit DAC 1 multiplexed charge output with variable shaping 20-200ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pC) Crosstalk < 1% Technology : AMS SiGe 0.35µm Submitted 13 june 05 Area 12 mm 2 Dissipation 130 mW @ VDD=3.5V Synoptic diagramm of MAROC1 Hold signal Variab le Gain Pream p. Variable Slow Shaper S&H Bipolar Fast Shaper 64Trigger outputs Gain correction 6 bits/channel discriminator threshold 10 bits DAC Multiplexed charge output 64 PM inputs 10 bit DAC ©N. Seguin (LAL)

36. 5 Feb 2007 Waclaw Karpinski 36 Next version – MAROC2 Hold signal Photomultiplier 64 channels Photons Variable Gain Preamp. Variable Slow Shaper 20-100 ns S&H Bipolar Fast Shaper Unipolar Fast Shaper Gain correction 64*6bits 3 discri thresholds (3*12 bits) Multiplexed Analog charge output LUCID S&H 3 DACs 12 bits 80 MHz encoder 64 Wilkinson 12 bit ADC 64 trigger outputs Multiplexed Digital charge output 64 inputs Substrate separation Unipolar fast shaper 3 discriminators 80MHz encoding 12bits Wilkinson ADC New features:

37. 5 Feb 2007 Waclaw Karpinski 37 SPIROC for AHCAL SiPM Si PM Integrated Read Out Chip (Mar 07) Chip fully dedicated to SiPMs developped after ECAL chip Internal DAC for SiPM gain adjustment (5V range) Auto-trigger (fast shaper + Discriminator) Internal TDC, 1 ns step Internal 12 bit ADC Power pulsing T&H x1 Variable gain Preamplifier Discri TDC 12-bit ADC 8 bit DAC (0-5V) in Fast Shaper Shaper t p ~30-40ns Auto-trigger 12-bit DAC Threshold Capacitance for AC coupling … Analogue Memory Charge Ouput Time Ouput

38. 5 Feb 2007 Waclaw Karpinski 38 SiPM - PEBS-TOF Crate C&DI - interface for higer DAQ SDR - data reduction board SFE - charge and time measurement SPT - pre-trigger SPSFE - voltage supply for Front End SBIAS - bias generator for SIPM Backplane SPSFESBIASSFTRSFESDRC&DI 654321

39. 5 Feb 2007 Waclaw Karpinski 39 PEBS Trigger Electronics generates Fast Trigger: 50-70 ns after the hit based on a coincidence between at least 3 out of 4 ToF planes evaluates signals from ToF and ECAL if any of predeterminated patterns of these signals occurs generates Level-1 trigger 1µs after the hit starts digitization and data flow for all subdetectors controls the BUSY signal to ensure that the event is collected from the complete detector

40. 5 Feb 2007 Waclaw Karpinski 40 PEBS-Trigger Crate TLV1 - level 1 trigger TTBX - fast trigger, fast in/out and logic JINJ - intermediate DAQ, 1CDDC, 24 links to sleeves 4 links to masters

41. 5 Feb 2007 Waclaw Karpinski 41 Summary

42. 5 Feb 2007 Waclaw Karpinski 42 Summary Power Consumption (ToF readout with PMs) SubsystemChannels Power FE [W] Power DAQ [W] Power PS [W] Power Total [W] TRD17927131131 Tracker4710494 47236 ECAL380088419 TOF64116832112 Trigger 5 Slow Control 213 Main DAQ 45 PDS 60 Contingency 100  610

43. 5 Feb 2007 Waclaw Karpinski 43 Summary TRD Readout boards used in AMS02 can be utilized without any changes for PEBS-TRD readout For Tracker and ECAL Front End new developments are necessary:  investigation of adequate readout chip  Front-End Hybrids  modifications of voltage supply boards for front end  new design of bias voltage generator boards  new backplanes Readout Architecture of TRD2 boards can be applied in PEBS Tracker and ECAL but the design of the readout boards must be slightly modified to much the detector granularity Two version of TOF electronics possible:  readout using PMs; AMS2 TOF electronics can be easily adapted to PEBS needs  readout using SiPMs; new designs necessary

44. 5 Feb 2007 Waclaw Karpinski 44 Expected total power dissipation amounts to ~ 600 W, including 100 W contingency Interfaces for power and interface for data transfer to Earth must be investigated Summary